Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS

1. A method for forming a dual channel device, comprising the steps of:

forming fins on a substrate, the fins comprising silicon (Si) fins in combination with silicon germanium (SiGe) fins as dual channels of an analog device and a logic device, with the analog device and the logic device each comprising an Si fin and a SiGe fin;

forming a silicon germanium oxide (SiGeOx) layer on the SiGe fins;

annealing the SiGeOx layer to form a Si-rich layer on the SiGe fins via a reaction between SiGeOx and SiGe; and

forming metal gates over the Si fins and over the Si-rich layer on the SiGe fins.

2. The method of claim 1 , wherein the Si-rich layer has a Si concentration of from about 80% to about 100%, and ranges therebetween.

3. The method of claim 1 , further comprising the step of:

forming shallow trench isolation (STI) regions in the substrate between the fins.

4. The method of claim 3 , further comprising the steps of:

depositing the SiGeOx layer onto the substrate over the fins and the STI regions between the fins;

masking the SiGeOx layer on the SiGe fins; and

removing the SiGeOx layer from the Si fins.

5. The method of claim 4 , wherein following the annealing, unreacted portions of the SiGeOx layer remain on the STI regions.

6. The method of claim 1 , further comprising the step of:

forming a chemical oxide on the Si fins.

7. The method of claim 6 , further comprising the steps of:

selectively masking the analog device;

forming the chemical oxide on the Si fin of the logic device; and

forming the chemical oxide on the Si-rich layer of the SiGe fin of the logic device.

8. The method of claim 1 , wherein the reaction forms an oxide layer, over the Si-rich layer, on the SiGe fins, the method further comprising the steps of:

forming a chemical oxide on the Si fin of the analog device, wherein the oxide layer and the chemical oxide serve as a first interfacial layer (IL) gate oxide of the analog device; and

depositing a second IL gate oxide over the first IL gate oxide in the analog device.

9. The method of claim 1 , further comprising the steps of:

forming dummy gates over the fins prior to the forming of the SiGeOx layer on the SiGe fins; and

replacing the dummy gates with the metal gates after the annealing has been performed.

10. The method of claim 9 , wherein the dummy gates are formed from a material selected from the group consisting of: poly-silicon, amorphous silicon, and combinations thereof.

11. The method of claim 1 , wherein the annealing is performed at a temperature of from about 1000° C. to about 1077° C., and ranges therebetween, for a duration of from about 1 second to about 5 seconds, and ranges therebetween.

12. The method of claim 11 , wherein the annealing is performed in an inert gas ambient.

13. The method of claim 1 , wherein the metal gates comprise:

a gate dielectric; and

a workfunction-setting metal disposed on the gate dielectric.

14. The method of claim 13 , wherein the gate dielectric is selected from the group consisting of: hafnium oxide (HfO 2 ), lanthanum oxide (La 2 O 3 ), and combinations thereof.

15. The method of claim 13 , wherein the workfunction-setting metal is selected from the group consisting of: titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al)-containing alloys, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), tantalum aluminide (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tungsten (W), and combinations thereof.