IP Library Granted Patent US 10,217,757
Granted Patent B2
US 10,217,757 · App. 15/934,437 · Granted Feb 26, 2019

Semiconductor memory device including a substrate, various interconnections, semiconductor member, charge storage member and a conductive member

Inventor: Yoshiro Shimojo (Yokkaichi, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L27/11548H01L27/11519H01L27/11526H01L27/11556H01L27/11565H01L27/11573H01L27/11575H01L27/11582
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Quick Facts
Patent No.
US 10,217,757
App. No.
15/934,437
Granted
Feb 26, 2019
Kind
B2
Abstract

According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.

Claims (10)

1. A semiconductor memory device, comprising:

a substrate;

a first interconnect provided on one side of the substrate in a first direction;

a second interconnect provided on the one side of the first interconnect;

a plurality of third interconnects extending in a second direction, being arranged to be separated from each other along the first direction, and being provided on the one side of the second interconnect, the second direction crossing the first direction;

a fourth interconnect provided on the one side of the third interconnects;

a semiconductor member extending in the first direction and piercing the plurality of third interconnects, one end portion of the semiconductor member being connected to the second interconnect;

a charge storage member provided between the semiconductor member and one of the plurality of third interconnects; and

a conductive member connected between the first interconnect and the fourth interconnect and insulated from the second interconnect and the plurality of third interconnects,

one of the plurality of third interconnects being disposed on two second-direction sides of the conductive member, and portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member being formed as one body.

Assignments (3)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
Priority Claims (1)
JP 2016-047644 · Mar 10, 2016 · national
Continuity (2)
Continuation 15455443 · Mar 10, 2017
Related Publication 20180211967A1 · Jul 26, 2018
Cited By (2)
US 12,327,757 US 12,408,344