Shift register, driving method thereof, gate driving circuit, and display apparatus

1. A shift register, comprising:

an input sub-circuit coupled to an input terminal and a pull-up node, and configured to charge the pull-up node under control of an input signal from the input terminal;

an output sub-circuit coupled to a clock signal terminal, the pull-up node, and an output terminal, and configured to transmit a clock signal from the clock signal terminal to the output terminal under control of the pull-up node; and

an output shaping sub-circuit coupled to the clock signal terminal, the output terminal, and a first voltage signal terminal, and configured to transmit a first voltage signal from the first voltage signal terminal to the output terminal under control of the clock signal,

wherein the output shaping sub-circuit comprises a first transistor, a second transistor and a third transistor,

wherein a control terminal of the first transistor is coupled to the clock signal terminal, a first terminal of the first transistor is coupled to a reference node, and a second terminal of the first transistor is coupled to the first voltage signal terminal,

wherein a control terminal of the second transistor is coupled to the reference node, a first terminal of the second transistor is coupled to the first voltage signal terminal, and a second terminal of the second transistor is coupled to the output terminal, and

wherein a control terminal and a first terminal of the third transistor are coupled to a second voltage signal terminal, and a second terminal of the third transistor is coupled to the reference node,

wherein in response to the clock signal being at a high level, the second transistor is controlled by only the first transistor, and the first voltage signal from the first voltage signal terminal is transmitted by the first transistor to the control terminal of the second transistor through the reference node,

wherein in response to the clock signal being at a low level, the second transistor is controlled by only the third transistor, and a second voltage signal from the second voltage signal terminal is transmitted by the third transistor to the control terminal of the second transistor through the reference node, and

wherein a turn-on resistance of the first transistor is less than that of the third transistor, and the reference node is only coupled to the first terminal of the first transistor, the control terminal of the second transistor and the second terminal of the third transistor, and is arranged separately from a portion, other than the output shaping sub-circuit, of the shift register, so that in response to the clock signal being at a high level, a potential at the reference node is only controlled by the first transistor, and in response to the clock signal being at a low level, a potential at the reference node is only controlled by the third transistor.

2. The shift register according to claim 1 , further comprising:

a reset sub-circuit coupled to a reset signal terminal, the pull-up node, and the first voltage signal terminal, and configured to provide the first voltage signal from the first voltage signal terminal to the pull-up node under control of a reset signal from the reset signal terminal;

a pull-up node control sub-circuit coupled to the pull-up node, a pull-down node and the first voltage signal terminal, and configured to provide the first voltage signal from the first voltage signal terminal to the pull-up node under control of the pull-down node;

a pull-down control sub-circuit coupled to the pull-down node, the first voltage signal terminal and the output terminal, and configured to provide the first voltage signal from the first voltage signal terminal to the output terminal under control of the pull-down node;

a first pull-down node control sub-circuit coupled to the pull-down node and the second voltage signal terminal, and configured to provide the second voltage signal from the second voltage signal terminal to the pull-down node; and

a second pull-down node control sub-circuit coupled to the pull-up node, the pull-down node, and the first voltage signal terminal, and configured to provide the first voltage signal from the first voltage signal terminal to the pull-down node under control of the pull-up node.

3. The shift register according to claim 1 , wherein the input sub-circuit comprises a fourth transistor, wherein:

a control terminal and a first terminal of the fourth transistor are coupled to the input terminal, and a second terminal of the fourth transistor is coupled to the pull-up node.

4. The shift register according to claim 2 , wherein the reset sub-circuit comprises a fifth transistor, wherein:

a control terminal of the fifth transistor is coupled to the reset signal terminal, a first terminal of the fifth transistor is coupled to the pull-up node, and a second terminal of the fifth transistor is coupled to the first voltage signal terminal.

5. The shift register according to claim 1 , wherein the output sub-circuit comprises a sixth transistor and a first capacitor, wherein:

a control terminal of the sixth transistor is coupled to the pull-up node, a first terminal of the sixth transistor is coupled to the clock signal terminal, and a second terminal of the sixth transistor is coupled to the output terminal; and

a first terminal of the first capacitor is coupled to the pull-up node, and a second terminal of the first capacitor is coupled to the output terminal.

6. The shift register according to claim 2 , wherein the pull-up node control sub-circuit comprises a seventh transistor, wherein:

a control terminal of the seventh transistor is coupled to the pull-down node, a first terminal of the seventh transistor is coupled to the pull-up node, and a second terminal of the seventh transistor is coupled to the first voltage signal terminal.

7. The shift register according to claim 2 , wherein the pull-down control sub-circuit comprises an eighth transistor, wherein:

a control terminal of the eighth transistor is coupled to the pull-down node, a first terminal of the eighth transistor is coupled to the output terminal, and a second terminal of the eighth transistor is coupled to the first voltage signal terminal.

8. The shift register according to claim 2 , wherein the first pull-down node control sub-circuit comprises a ninth transistor and a tenth transistor, wherein:

a control terminal of the ninth transistor is coupled to a second terminal of the tenth transistor, a first terminal of the ninth transistor is coupled to the second voltage signal terminal, and a second terminal of the ninth transistor is coupled to the pull-down node; and

a control terminal and a first terminal of the tenth transistor are coupled to the second voltage signal terminal.

9. The shift register according to claim 8 , wherein the second pull-down node control sub-circuit comprises an eleventh transistor and a twelfth transistor, wherein:

a control terminal of the eleventh transistor is coupled to the pull-up node, a first terminal of the eleventh transistor is coupled to the pull-down node, and a second terminal of the eleventh transistor is coupled to the first voltage signal terminal; and

a control terminal of the twelfth transistor is coupled to the pull-up node, a first terminal of the twelfth transistor is coupled to the control terminal of the ninth transistor, and a second terminal of the twelfth transistor is coupled to the first voltage signal terminal.

10. The shift register according to claim 2 , wherein all transistors of the sub-circuits are N-type transistors, the first voltage signal is a low level signal and the second voltage signal is a high level signal.

11. A gate driving circuit comprising a plurality of cascaded shift registers according to claim 1 .

12. A display apparatus comprising the gate driving circuit according to claim 11 .

13. A driving method of the shift register according to claim 1 , comprising:

in a first phase, charging, by the input sub-circuit, the pull-up node under control of the input signal;

in a second phase, transmitting, by the output sub-circuit, the clock signal to the output terminal under control of the pull-up node; and

in a third phase, transmitting, by the output shaping sub-circuit, the first voltage signal to the output terminal under control of the clock signal.

14. The method of claim 13 , wherein a sum of the first phase, the second phase, and the third phase is approximately equal to one clock cycle.

15. A gate driving circuit comprising a plurality of cascaded shift registers according to claim 2 .

16. A display apparatus comprising the gate driving circuit according to claim 15 .

17. A driving method of the shift register according to claim 2 , comprising:

in a first phase, charging, by the input sub-circuit, the pull-up node under control of the input signal;

in a second phase, transmitting, by the output sub-circuit, the clock signal to the output terminal under control of the pull-up node; and

in a third phase, transmitting, by the output shaping sub-circuit, the first voltage signal to the output terminal under control of the clock signal.

18. The method according to claim 17 , wherein a sum of the first phase, the second phase, and the third phase is approximately equal to one clock cycle.

19. A gate driving circuit comprising a plurality of cascaded shift registers according to claim 3 .

20. A shift register, comprising:

an input sub-circuit coupled to an input terminal and a pull-up node, and configured to charge the pull-up node under control of an input signal from the input terminal;

an output sub-circuit coupled to a clock signal terminal, the pull-up node, and an output terminal, and configured to transmit a clock signal from the clock signal terminal to the output terminal under control of the pull-up node; and

an output shaping sub-circuit coupled to the clock signal terminal, the output terminal, and a first voltage signal terminal, and configured to transmit a first voltage signal from the first voltage signal terminal to the output terminal under control of the clock signal,

wherein the output shaping sub-circuit comprises a first transistor, a second transistor and a third transistor;

wherein a control terminal of the first transistor is coupled to the clock signal terminal, a first terminal of the first transistor is coupled to a reference node, and a second terminal of the first transistor is coupled to the first voltage signal terminal;

wherein a control terminal of the second transistor is coupled to the reference node, a first terminal of the second transistor is coupled to the first voltage signal terminal, and a second terminal of the second transistor is coupled to the output terminal; and

wherein a control terminal and a first terminal of the third transistor are coupled to a second voltage signal terminal, and a second terminal of the third transistor is coupled to the reference node,

wherein in response to the clock signal being at a high level, the second transistor is controlled by only the first transistor, and the first voltage signal from the first voltage signal terminal is transmitted by the first transistor to the control terminal of the second transistor through the reference node; and

wherein in response to the clock signal being at a low level, the second transistor is controlled by only the third transistor, and a second voltage signal from the second voltage signal terminal is transmitted by the third transistor to the control terminal of the second transistor through the reference node,

wherein the shift register further comprises:

a reset sub-circuit coupled to a reset signal terminal, the pull-up node, and the first voltage signal terminal, and configured to provide the first voltage signal from the first voltage signal terminal to the pull-up node under control of a reset signal from the reset signal terminal;

a pull-up node control sub-circuit coupled to the pull-up node, a pull-down node and the first voltage signal terminal, and configured to provide the first voltage signal from the first voltage signal terminal to the pull-up node under control of the pull-down node;

a pull-down control sub-circuit coupled to the pull-down node, the first voltage signal terminal and the output terminal, and configured to provide the first voltage signal from the first voltage signal terminal to the output terminal under control of the pull-down node;

a first pull-down node control sub-circuit coupled to the pull-down node and the second voltage signal terminal, and configured to provide a second voltage signal from the second voltage signal terminal to the pull-down node; and

a second pull-down node control sub-circuit coupled to the pull-up node, the pull-down node, and the first voltage signal terminal, and configured to provide the first voltage signal from the first voltage signal terminal to the pull-down node under control of the pull-up node,

wherein the input sub-circuit comprises a fourth transistor, a control terminal and a first terminal of the fourth transistor being coupled to the input terminal, and a second terminal of the fourth transistor being coupled to the pull-up node;

wherein the reset sub-circuit comprises a fifth transistor, a control terminal of the fifth transistor being coupled to the reset signal terminal, a first terminal of the fifth transistor being coupled to the pull-up node, and a second terminal of the fifth transistor being coupled to the first voltage signal terminal;

wherein the output sub-circuit comprises a sixth transistor and a first capacitor, a control terminal of the sixth transistor being coupled to the pull-up node, a first terminal of the sixth transistor being coupled to the clock signal terminal, a second terminal of the sixth transistor being coupled to the output terminal, a first terminal of the first capacitor being coupled to the pull-up node, and a second terminal of the first capacitor being coupled to the output terminal;

wherein the pull-up node control sub-circuit comprises a seventh transistor, a control terminal of the seventh transistor being coupled to the pull-down node, a first terminal of the seventh transistor being coupled to the pull-up node, and a second terminal of the seventh transistor being coupled to the first voltage signal terminal;

wherein the pull-down control sub-circuit comprises an eighth transistor, a control terminal of the eighth transistor being coupled to the pull-down node, a first terminal of the eighth transistor being coupled to the output terminal, and a second terminal of the eighth transistor being coupled to the first voltage signal terminal;

wherein the first pull-down node control sub-circuit comprises a ninth transistor and a tenth transistor, a control terminal of the ninth transistor being coupled to a second terminal of the tenth transistor, a first terminal of the ninth transistor being coupled to the second voltage signal terminal, a second terminal of the ninth transistor being coupled to the pull-down node, and a control terminal and a first terminal of the tenth transistor being coupled to the second voltage signal terminal;

wherein the second pull-down node control sub-circuit comprises an eleventh transistor and a twelfth transistor, a control terminal of the eleventh transistor being coupled to the pull-up node, a first terminal of the eleventh transistor being coupled to the pull-down node, a second terminal of the eleventh transistor being coupled to the first voltage signal terminal, a control terminal of the twelfth transistor being coupled to the pull-up node, a first terminal of the twelfth transistor being coupled to the control terminal of the ninth transistor, and a second terminal of the twelfth transistor being coupled to the first voltage signal terminal; and

wherein a turn-on resistance of the first transistor is less than that of the third transistor, and the reference node is only coupled to the first terminal of the first transistor, the control terminal of the second transistor and the second terminal of the third transistor, and is arranged separately from a portion, other than the output shaping sub-circuit, of the shift register, so that in response to the clock signal being at a high level, a potential at the reference node is only controlled by the first transistor, and in response to the clock signal being at a low level, a potential at the reference node is only controlled by the third transistor.