Dynamic random access memory structure and method for forming the same
The present invention provides a dynamic random access memory structure, comprising a substrate defining a cell region and a peripheral region on the substrate, a shallow trench isolation structure located in the peripheral region adjacent to the cell region, wherein the shallow trench isolation structure has a concave top surface, a first dummy bit line gate located within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate located in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.
1. A dynamic random access memory (DRAM) structure, comprising:
a substrate having a cell region and a peripheral region defined thereon;
a plurality of buried word lines, located in the cell region of the substrate;
a shallow trench isolation structure located in the peripheral region adjacent to the cell region, wherein the shallow trench isolation structure has a concave top surface;
a first dummy bit line gate located on the shallow trench isolation structure within the peripheral area; and
a second dummy bit line gate located in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.
2. The dynamic random access memory structure of claim 1 , wherein the first dummy bit line gate is completely located on the shallow trench isolation structure.
3. The dynamic random access memory structure of claim 1 , further comprising a dielectric layer disposed on the substrate and on the shallow trench isolation structure.
4. The dynamic random access memory structure of claim 3 , wherein a portion of the dielectric layer is located between the first dummy bit line gate and the second dummy bit line gate.
5. The dynamic random access memory structure of claim 1 , wherein the first dummy bit line gate contacts the second dummy bit line gate directly.
6. The dynamic random access memory structure of claim 1 , wherein the first dummy bit line gate comprises a stacked structure of an amorphous silicon layer, a barrier layer and a metal layer.