IP Library › Granted Patent US 10,867,844
Granted Patent B2
US 10,867,844 · App. 15/939,025 · Granted Dec 15, 2020

Wet cleaning with tunable metal recess for VIA plugs

Inventors: Yu Shih Wang (Tainan, TW); Shian Wei Mao (Taipei, TW); Ming-Hsi Yeh (Hsinchu, TW); Kuo-Bin Huang (Hsinchu County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L21/76831H01L21/76805H01L21/76877H01L23/5226H01L23/564
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Quick Facts
Patent No.
US 10,867,844
App. No.
15/939,025
Granted
Dec 15, 2020
Kind
B2
Abstract

In one exemplary aspect, a method comprises providing a semiconductor structure having a substrate, one or more first dielectric layers over the substrate, a first metal plug in the one or more first dielectric layers, and one or more second dielectric layers over the one or more first dielectric layers and the first metal plug. The method further comprises etching a via hole into the one or more second dielectric layers to expose the first metal plug, etching a top surface of the first metal plug to create a recess thereon, and applying a metal corrosion protectant comprising a metal corrosion inhibitor to the top surface of the first metal plug.

Claims (36)

1. A method, comprising:

providing a semiconductor structure having a first metal plug disposed in a first dielectric layer and a second dielectric layer disposed over the first dielectric layer and the first metal plug;

performing a first etching process to etch a via hole into the second dielectric layer to form an exposed first metal plug disposed in the first dielectric layer;

after the first etching process, performing a second etching process different from the first etching process to etch the exposed first metal plug via the via hole and form a recessed top surface of the exposed first metal plug; and

applying a metal corrosion protectant that includes a metal corrosion inhibitor to the recessed top surface of the exposed first metal plug, wherein the metal corrosion inhibitor is configured to decrease a corrosion rate of the exposed first metal plug during a subsequent process to which the first metal plug is exposed.

2. The method of claim 1 , wherein dimensions of the recessed top surface of the exposed first metal plug are controlled by adjusting a time, a temperature, or both the time and the temperature for the second etching process.

3. The method of claim 1 , wherein the metal corrosion protectant is applied to the recessed top surface of the exposed first metal plug after the recessed top surface of the exposed first metal plug has reached a pre-defined target profile.

4. The method of claim 3 , wherein the pre-defined target profile is a bowl shape with a substantially smooth surface.

5. The method of claim 1 , further comprising:

rinsing the exposed first metal plug via the via hole to remove a wet etchant used in the second etching process; and

forming a second metal plug in the via hole, wherein the second metal plug contacts the recessed top surface of the exposed first metal plug.

6. The method of claim 5 , wherein the second etching process uses an isotropic etching process.

7. The method of claim 5 , wherein the wet etchant includes carbon dioxide (CO 2 ) blended deionized (DI) water, ozone (O 3 ) blended DI water, hydrogen peroxide (H 2 O 2 ) blended DI water, or a combination thereof.

8. The method of claim 5 , wherein the rinsing of the exposed first metal plug uses isopropyl alcohol (IPA), acetone, methanol, or a combination thereof.

9. The method of claim 1 , wherein the via hole is a first via hole, the method further comprising performing a third etching process, simultaneously with the first etching process, to etch a second via hole into the second dielectric layer to expose the first metal plug disposed in the first dielectric layer.

10. The method of claim 1 , wherein the via hole has a bottom opening width and a top opening width, and wherein the bottom opening width is between 90% and 95% of the top opening width.

11. A method, comprising:

providing a semiconductor device having a first lower plug disposed in a first interlayer dielectric (ILD) layer and a second ILD layer disposed over the first ILD layer and the first lower plug;

etching a first via hole into the second ILD layer to form an at least partially exposed first lower plug disposed in the first ILD layer; and

performing a wet cleaning process via the first via hole to form a recessed top surface of the exposed first lower plug, wherein the wet cleaning process includes:

applying a wet etchant to the exposed first lower plug to form the recessed top surface of the exposed first lower plug,

applying a metal corrosion inhibitor to the recessed top surface of the exposed first lower plug, wherein the metal corrosion inhibitor is configured to decrease a corrosion rate of the exposed first lower plug during a rinsing process and a drying process, and

performing the rinsing process and the drying process on the exposed first lower plug.

12. The method of claim 11 , further comprising filling an upper plug into the first via hole, wherein the first lower plug and the upper plug include different materials.

13. The method of claim 11 , wherein dimensions of the recessed top surface of the exposed first lower plug are tunable by controlling a time, a temperature, or both the time and the temperature of the wet cleaning process.

14. The method of claim 13 , wherein the metal corrosion inhibitor is applied to the recessed top surface of the exposed first lower plug after the dimensions of the recessed top surface of the exposed first lower plug have reached pre-defined values.

15. The method of claim 11 , wherein the wet etchant comprises carbon dioxide (CO 2 ) blended deionized (DI) water, ozone (O 3 ) blended DI water, hydrogen peroxide (H 2 O 2 ) blended DI water, or a combination thereof.

16. The method of claim 11 , further comprising etching a second via hole into the second ILD layer to form an at least partially exposed second lower plug disposed in the first ILD layer, wherein the wet cleaning process further forms a recessed top surface of the exposed second lower plug, and wherein dimensions of the recessed top surface of the exposed second lower plug are substantially equal to the dimensions of the recessed top surface of the exposed first lower plug.

17. A method, comprising:

etching a first metal plug using a wet etchant to form a recessed top surface of the first metal plug;

after the etching of the first metal plug, applying a metal corrosion inhibitor to the recessed top surface of the first metal plug, wherein the metal corrosion inhibitor is configured to decrease a corrosion rate of the first metal plug during a rinsing process and a drying process; and

after the applying of the metal corrosion inhibitor, performing the rinsing process and the drying process on the first metal plug.

18. The method of claim 17 , further comprising:

before the etching of the first metal plug, etching a via hole into a dielectric layer disposed over the first metal plug.

19. The method of claim 18 , wherein the rinsing process removes a residue formed during the etching of the via hole.

20. The method of claim 17 , wherein a time, a temperature, or both the time and the temperature are controlled during each of the etching of the first metal plug, the applying of the metal corrosion inhibitor, and the rinsing process to adjust a profile of the recessed top surface of the first metal plug.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2018
From: WANG, YU SHIH; MAO, SHIAN WEI; YEH, MING-HSI; HUANG, KUO-BIN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 046027/0740 →
Continuity (1)
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