Semiconductor package

1. A semiconductor package comprising:

an organic interposer including insulating layers and wiring layers disposed on the insulating layers;

a semiconductor chip disposed on one surface of the organic interposer and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;

an encapsulant disposed on the organic interposer and encapsulating at least portions of the semiconductor chip;

a passivation layer disposed on another surface of the organic interposer opposing the one surface of the organic interposer on which the semiconductor chip is disposed and having openings extending to at least portions of the wiring layer; and

an underbump metallurgy (UBM) layer including UBM pads disposed on the passivation layer and UBM vias disposed in the openings and connecting the UBM pads and the wiring layer to each other,

wherein at least one groove portion is disposed in an outer circumferential surface of the UBM pad.

2. The semiconductor package of claim 1 , wherein a distance from a center of the UBM pad to an outer circumferential surface of a region in which the groove portion of the UBM pad is not disposed is greater than a distance from the center of the UBM pad to an outer circumferential surface of a region in which the groove portion of the UBM pad is disposed.

3. The semiconductor package of claim 2 , further comprising electrical connection structures disposed on the passivation layer and connected to the UBM pads,

wherein the groove portion is filled with the electrical connection structure.

4. The semiconductor package of claim 1 , wherein at least portions of the UBM pad protrude below a lower surface of the passivation layer.

5. The semiconductor package of claim 4 , wherein a width of an upper surface of the UBM via in contact with the wiring layer'is smaller than a width of a lower surface of the UBM via in contact with the UBM pad.

6. The semiconductor package of claim 1 , wherein at least portions of the UBM pad are embedded in the passivation layer.

7. The semiconductor package of claim 6 , wherein a width of an upper surface of the UBM via in contact with the wiring layer is greater than a width of a lower surface of the UBM via in contact with the UBM pad.

8. The semiconductor package of claim 1 , wherein a conductive bump is further disposed on the connection pad of the semiconductor chip.

9. The semiconductor package of claim 8 , wherein the conductive bump includes a low melting point metal.

10. The semiconductor package of claim 1 , wherein the semiconductor chip includes a graphics processing unit (GPU) and a plurality of high bandwidth memories (HBMs) disposed in the vicinity of the GPU, and

the GPU and the HBMs are electrically connected to each other through the wiring layer.

11. The semiconductor package of claim 1 , wherein the inactive surface of the semiconductor chip is exposed from the encapsulant.

12. A semiconductor package comprising:

a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;

an encapsulant encapsulating at least portions of the semiconductor chip;

a connection member disposed on the active surface of the semiconductor chip and including a wiring layer electrically connected to the connection pads;

a passivation layer disposed on the connection member and having openings extending to at least portions of the wiring layer; and

a UBM layer including UBM pads disposed on the passivation layer and UBM vias disposed in the openings and connecting the UBM pads and the exposed wiring layer to each other,

wherein a boundary of each UBM pad, on the passivation layer, includes at least one concave portion.

13. The semiconductor package of claim 12 , wherein the UBM pad has a shape that includes a plurality of protrusions spaced apart from each other and extending from central portion of the UBM pad.

14. The semiconductor package of claim 12 , wherein a surface of the passivation layer is exposed in the at least one concave portion of the boundary of the UBM pad.

15. The semiconductor package of claim 14 , further comprising a conductive bump disposed on the UBM pad of the semiconductor chip, and extending in the at least one concave portion of the boundary of the UBM pad.

16. An interposer configured to have a semiconductor chip mounted on an upper surface thereof, comprising:

an insulating material forming a body of the interposer;

a plurality of wiring layers disposed in an insulating material of the body, and disposed on the upper surface of the interposer to be connected to connections pads of the semiconductor chip;

a plurality of vias penetrating through the insulating material of the body to interconnect adjacent wiring layers of the plurality of wiring layers;

a passivation layer disposed on a lower surface of the interposer opposite to the upper surface and having a plurality of openings each extending to a wiring layer; and

at least one UBM pad disposed on a lower surface of the passivation layer, and connected to the wiring layer through a connection via extending through an opening of the plurality of openings,

wherein an outline of an area occupied by the at least one UBM pad on the lower surface of the passivation layer includes at least one concave portion.

17. The interposer of claim 16 , wherein the an area occupied by the at least one UBM pad has a shape that includes a plurality of protrusions spaced apart from each other by the at least one concave portion.

18. The interposer of claim 16 , wherein the lower surface of the passivation layer is exposed in the at least one concave portion of the boundary of the UBM pad.

19. The interposer of claim 16 , wherein the area occupied by the at least one UBM pad on the lower surface of the passivation layer includes a plurality of evenly-spaced concave portions disposed along an outer periphery of the area.

20. The interposer of claim 16 , wherein at least portions of side surfaces of the at least one UBM pad are spaced apart from the passivation layer.