IP Library Granted Patent US 10,374,080
Granted Patent B2
US 10,374,080 · App. 15/943,696 · Granted Aug 6, 2019

Semiconductor device and method of manufacturing semiconductor device

Inventors: Naoyuki Ohse (Matsumoto, JP); Yusuke Kobayashi (Tsukuba, JP); Takahito Kojima (Matsumoto, JP); Shinsuke Harada (Tsukuba, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L29/7813H01L29/0623H01L29/1608H01L29/41766H01L29/47H01L29/66068H01L29/7806H01L29/872
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Quick Facts
Patent No.
US 10,374,080
App. No.
15/943,696
Filed
Apr 2, 2018
Granted
Aug 6, 2019
Kind
B2
Examiner
WARD, ERIC A
Art Unit
2891
USPC
257/330
Abstract

On a front surface of a semiconductor base, an n − -type drift layer, a p-type base layer, an n ++ -type source region, and a gate trench and a contact trench penetrating the n ++ -type source region and the p-type base layer and reaching the n − -type drift layer are provided. The contact trench is provided separated from the gate trench. A Schottky metal is embedded in the contact trench and forms a Schottky contact with the n − -type drift layer at a side wall of the contact trench. An ohmic metal is provided at a bottom of the contact trench and forms an ohmic contact with the n − -type drift layer.

Claims (21)

1. A semiconductor device, comprising:

semiconductor substrate of a first conductivity type;

a first semiconductor layer having a first sub-region of the first conductivity type provided on a front surface of the semiconductor substrate;

a second semiconductor layer having a second sub-region of a second conductivity type, the second semiconductor layer provided on a first side of the first semiconductor layer opposite a second side of the first semiconductor layer facing the semiconductor substrate;

a first semiconductor region of the first conductivity type selectively provided in the second semiconductor layer, an impurity concentration of the first semiconductor region being higher than an impurity concentration of the semiconductor substrate;

a first trench penetrating the first semiconductor region and the second semiconductor layer, and reaching the first semiconductor layer;

a gate electrode provided in the first trench, on a gate insulating film;

an interlayer insulating film provided on the gate electrode;

a first electrode in contact with the first semiconductor region and the second semiconductor layer;

a second electrode provided on a rear surface of the semiconductor substrate;

a second trench separated from the first trench, the second trench penetrating the first semiconductor region and the second semiconductor layer, and reaching the first semiconductor layer;

a first metal electrode embedded in the second trench, the first metal electrode forming a Schottky contact with the first semiconductor layer at a side wall of the second trench; and

a second metal electrode forming an ohmic contact with the first semiconductor layer at a bottom of the second trench.

2. The semiconductor device according to claim 1 , wherein

the first metal electrode occupies at least 30% of an internal volume of the second trench.

3. The semiconductor device according to claim 1 , wherein

the first metal electrode is embedded from a bottom of the second trench to at least an interface of the second semiconductor layer and the first semiconductor region.

4. The semiconductor device according to claim 1 , wherein

the first metal electrode protrudes outwardly from the second trench.

5. The semiconductor device according to claim 1 , wherein

the first metal electrode protrudes outwardly from the second trench and covers the interlayer insulating film and the first electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2018
From: OHSE, NAOYUKI; KOBAYASHI, YUSUKE; KOJIMA, TAKAHITO; HARADA, SHINSUKE
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 045689/0283 →
Priority Claims (1)
JP 2017-084063 · Apr 20, 2017 · national
Continuity (1)
Related Publication 20180308975A1 · Oct 25, 2018
Cited By (2)
US 12,302,614 US 12,684,837