Device with data processing engine array that enables partial reconfiguration

1. A device comprising:

a processor system; and

an array of data processing engines (DPEs) communicatively coupled to the processor system, each of the DPEs comprising a DPE processor and a DPE interconnect, the DPE processor having an architecture configured to support an instruction set and being configured to execute executable program code according to the instruction set, the processor system being configured to transmit configuration data to the array of DPEs, each of the DPEs being independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE, the array of DPEs enabling, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

2. The device of claim 1 , wherein the DPE interconnect of each of the DPEs includes:

a stream switch operable to be configured to communicate application data with a neighboring array component; and

a memory mapped switch configured to communicate the configuration data via memory mapped transactions with a neighboring array component.

3. The device of claim 1 further comprising:

a network coupled to the processor system; and

a system interface circuit coupled to the network and to the array of DPEs, the system interface circuit comprising tiles, each tile being coupled to a column of DPEs of the array of DPEs, the processor system being configured to transmit the configuration data to the array of DPEs via the network and the system interface circuit.

4. The device of claim 1 , wherein each of the DPEs comprises:

program memory configured to store executable program code that is according to the instruction set and is executable by the DPE processor of the respective DPE; and

configuration registers configured to store interconnect data that configures the DPE interconnect of the respective DPE for routing communications via the DPE interconnect.

5. The device of claim 1 , wherein a first kernel implemented by the first subset of the DPEs of the array of DPEs and a second kernel implemented by the second subset of the DPEs of the array of DPEs do not have a shared hardware resource, and no data and/or control dependency exists between the first kernel and the second kernel.

6. The device of claim 1 , wherein the first kernel implemented by the first subset of the DPEs of the array of DPEs and a second kernel implemented by the second subset of the DPEs of the array of DPEs have a shared hardware resource, and no data and/or control dependency exists between the first kernel and the second kernel.

7. The device of claim 1 , wherein the first kernel implemented by the first subset of the DPEs of the array of DPEs and a second kernel implemented by the second subset of the DPEs of the array of DPEs do not have a shared hardware resource, and a data and/or control dependency exists between the first kernel and the second kernel.

8. The device of claim 1 , wherein the first kernel implemented by the first subset of the DPEs of the array of DPEs and a second kernel implemented by the second subset of the DPEs of the array of DPEs have a shared hardware resource, and a data and/or control dependency exists between the first kernel and the second kernel.

9. The device of claim 1 , wherein after reconfiguring the second subset of the DPEs of the array of DPEs:

a data flow to or from one of the first subset of the DPEs or the second subset of the DPEs is through the DPE interconnect of respective one or more of the DPEs of the other one of the first subset of the DPEs or the second subset of the DPEs.

10. The device of claim 1 , wherein after reconfiguring the second subset of the DPEs of the array of DPEs:

application and/or control data generated by one of the first subset of the DPEs or the second subset of the DPEs is received and processed by the other one of the first subset of the DPEs or the second subset of the DPEs.

11. A method for operating a device, the method comprising:

configuring a first subset of an array of data processing engines (DPEs), using a processor system, to implement a first kernel, each of the DPEs comprising a DPE processor and a DPE interconnect, the DPE processor having an architecture configured to support an instruction set and being configured to execute executable program code according to the instruction set, each of the DPEs being independently configurable based on configuration data received at the respective DPE via the DPE interconnect of the respective DPE;

operating the first kernel on the first subset of the array of DPEs; and

without modifying operation of the first kernel on the first subset of the array of DPEs, configuring a second subset of the array of DPEs, using the processor system, to implement a second kernel.

12. The method of claim 11 , wherein:

the processor system is coupled to the array of DPEs via a network and a system interface circuit;

the system interface circuit comprises tiles, and each tile is connected to a column of DPEs of the array of DPEs;

the DPE interconnect of each of the DPEs includes a memory mapped switch connected to respective neighboring DPEs and/or tile in the respective column, and includes a stream switch connected to respective neighboring DPEs and/or tile;

each of the DPEs comprises:

program memory configured to store executable program code that is according to the instruction set and is executable by the DPE processor of the respective DPE; and

configuration registers configured to store interconnect data that configures the stream switch of the respective DPE for routing communications via the stream switch; and

configuring the second subset comprises:

transmitting configuration data from the processor system via the network to the system interface circuit;

propagating the configuration data to one or more of the tiles corresponding to respective columns of the second subset;

communicating the configuration data from the respective one or more of the tiles to target ones of the DPEs of the second subset via the memory mapped switches of the target ones of the DPEs and intervening DPEs between the target ones of the DPEs and the respective one or more of the tiles; and

storing executable program code of the configuration data in the program memory of the target ones of the DPEs and interconnect data of the configuration data in the configuration registers of the target ones of the DPEs, the stored executable program code being according to the instruction set.

13. The method of claim 11 further comprising operating the second kernel, wherein while operating the second kernel:

data flow to or from the first kernel is not through the second subset of the array of DPEs;

data flow to or from the second kernel is not through the first subset of the array of DPEs;

data flow to and processed by the first kernel is not generated by the second kernel operating on the second subset of the array of DPEs; and

data flow to and processed by the second kernel is not generated by the first kernel operating on the first subset of the array of DPEs.

14. The method of claim 11 further comprising operating the second kernel, wherein while operating the second kernel:

data flow to or from one of the first kernel or the second kernel is through the second subset of the array of DPEs or the first subset of the array of DPEs, respectively.

15. The method of claim 11 further comprising operating the second kernel, wherein while operating the second kernel, data flow to and processed by one of the first kernel or the second kernel is generated by the other one of the first kernel or the second kernel.

16. A device comprising:

an array of data processing engines (DPEs), each of the DPEs comprising a DPE processor, program memory, a DPE interconnect, and configuration registers, wherein:

the DPE processor has an architecture configured to support an instruction set and is configured to execute executable program code according to the instruction set;

the program memory is configured to store executable program code that is according to the instruction set and is executable by the DPE processor of the respective DPE;

the DPE interconnect includes a stream switch and a memory mapped switch;

the memory mapped switch is configured to route a memory mapped transaction based on an address of a memory space; and

the configuration registers are configured to store interconnect data that configures the stream switch of the respective DPE for routing communications via the stream switch of the respective DPE; and

a system interface circuit comprising tiles, each tile being connected to a respective adjacent DPE of the array of DPEs; and

a processor system coupled to the system interface circuit, the processor system being operable to configure a first subset of the DPEs independently of a second subset of the DPEs, wherein:

the processor system is operable to transmit configuration data to the system interface circuit;

the system interface circuit is operable to propagate the configuration data to one or more of the tiles that provide an interface for the first subset of the DPEs;

the one or more of the tiles is operable to direct the configuration data to target ones of the DPEs of the first subset of the DPEs via the memory mapped switches of the target ones of the DPEs and intervening DPEs between the target ones of the DPEs and the respective one or more of the tiles;

executable program code of the configuration data is written to the program memory of the target ones of the DPEs; and

interconnect data of the configuration data is written to the configuration registers of the target ones of the DPEs.

17. The device of claim 16 further comprising a network, wherein the processor system is connected to the network, and the network is connected to the system interface circuit.

18. The device of claim 16 , wherein after configuring the first subset of the DPEs:

no stream switch of the second subset of the DPEs is configured to pass application data through the respective stream switch towards or from the first subset of the DPEs; and

no stream switch of the first subset of the DPEs is configured to pass application data through the respective stream switch towards or from the second subset of the DPEs.

19. The device of claim 16 , wherein after configuring the first subset of the DPEs:

at least one stream switch of the first subset of the DPEs is configured to pass application data through the respective stream switch towards or from the second subset of the DPEs; or

at least one stream switch of the second subset of the DPEs is configured to pass application data through the respective stream switch towards or from the first subset of the DPEs.

20. The device of claim 16 , wherein after configuring the first subset of the DPEs:

the first subset of the DPEs is configured to receive and process application data generated by the second subset of the DPEs; or

the second subset of the DPEs is configured to receive and process application data generated by the first subset of the DPEs.