Data processing engine tile architecture for an integrated circuit
An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes: a core; a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory; streaming interconnect coupled to the DMA circuitry and the core; and memory-mapped interconnect coupled to the core, the memory, and the support circuitry.
1. A data processing engine (DPE) for a DPE array in an integrated circuit (IC), comprising:
a core including compute circuitry and a program memory;
a memory module including:
a data memory comprising one or more memory banks;
a first interface directly connected to the core;
a second interface directly connected to a respective at least one additional core external to the DPE;
hardware lock circuitry coupled to the data memory and configured to lock memory of the one or more memory banks so that the locked memory is accessible only to one of: the core on the DPE or the at least one additional core external to the DPE;
arbitration logic for each of the one or more memory banks, wherein the arbitration logic is configured to control which of the first interface or second interface has access to each of the one or more memory banks, and wherein the arbitration logic is further configured to generate a first signal indicating a memory collision in response to detecting the core is attempting to access a same memory bank of the one or more memory banks which at least one additional core external to the DPE is accessing;
a stall circuit coupled to the compute circuitry and configured to provide a stall signal to the compute circuitry, wherein the stall signal is configured to stall the compute circuitry in the core in response to the first signal; and
direct memory access (DMA) circuitry coupled to the data memory;
streaming interconnect coupled to the DMA circuitry and the core; and
memory-mapped interconnect coupled to the core and the memory module.
2. The DPE of claim 1 further comprising debug circuitry coupled to the core and the memory module.
3. The DPE of claim 1 , wherein the one or more memory banks are respective one or more random access memory (RAM) banks, the memory module further including arbitration logic configured to arbitrate access to the one or more RAM banks.
4. The DPE of claim 3 , wherein the hardware lock circuitry is configured to lock access to the one or more RAM banks by the core, a core in another DPE in the DPE array, and the DMA circuitry.
5. The DPE of claim 4 , wherein the hardware lock circuitry is configured to provide synchronization between the core and at least one other core in at least one other DPE in the DPE array.
6. The DPE of claim 1 , wherein the streaming interconnect includes a stream switch having at least one connection to at least one additional DPE in the DPE array.
7. The DPE of claim 6 , wherein the stream switch includes a connection to the core.
8. The DPE of claim 1 , wherein the streaming interconnect includes a plurality of stream switches each having at least one connection to a different DPE in the DPE array in a different direction.
9. The DPE of claim 1 , wherein the memory-mapped interconnect includes a memory-mapped switch having at least one connection to at least one additional DPE in the DPE array.
10. The DPE of claim 1 , wherein the core includes a cascading interface directly connected to another core disposed in another DPE in the DPE array.
11. The DPE of claim 1 , wherein the core includes a plurality of registers coupled to the memory-mapped interconnect.
12. The DPE of claim 1 , wherein the compute circuitry comprises a very long instruction word (VLIW) processor, a single instruction, multiple data (SIMD) processor, or a VLIW SIMD processor.
13. The DPE of claim 1 , wherein the DMA circuitry includes a first DMA circuit having an output coupled to the streaming interconnect and an input coupled to the data memory, and a second DMA circuit having an input coupled to the streaming interconnect and an output coupled to the data memory.
14. The DPE of claim 1 , the arbitration logic is configured to control access to the respective memory bank by the first interface and the second interface.
15. The DPE of claim 1 , wherein the stall circuit comprises a plurality of inputs, one of the plurality of inputs coupled to arbitration logic, and the stall circuit is configured to receive a first signal indicative of a memory collision from the arbitration logic.
16. The DPE of claim 1 , wherein the stall circuit comprises:
an input to a processor subsystem;
an input to a stream switch connected to the DMA circuitry and the core;
an input to a register programmed through the memory-mapped interconnect;
an input to debug circuitry coupled to the core and the memory module; and
an input coupled to the hardware lock circuitry.
17. An integrated circuit (IC), comprising:
a data processing engine (DPE) array having a plurality of DPEs, each DPE of the DPEs comprising:
a core including compute circuitry and a program memory;
a memory module including:
a data memory comprising one or more memory banks;
a first interface directly connected to the core;
a second interface directly connected to a respective at least one additional core of a different DPE of the DPE array;
hardware lock circuitry coupled to the data memory and configured to lock memory of the one or more memory banks so that the locked memory is accessible only to one of: the core on the DPE or the at least one additional core external to the DPE;
arbitration logic for each of the one or more memory banks, wherein the arbitration logic is configured to control which of the first interface or second interface has access to each of the one or more memory banks, and wherein the arbitration logic is further configured to generate a first signal indicating a memory collision in response to detecting the core is attempting to access a same memory bank of the one or more memory banks which at least one additional core external to the DPE is accessing;
a stall circuit coupled to the compute circuitry and configured to provide a stall signal to the compute circuitry, wherein the stall signal is configured to stall the compute circuitry in the core in response to the first signal; and
direct memory access (DMA) circuitry coupled to the data memory;
streaming interconnect coupled to the DMA circuitry and the core; and
memory-mapped interconnect coupled to the core and the memory module.
18. The IC of claim 17 , wherein the compute circuitry comprises a very long instruction word (VLIW) processor, a single instruction, multiple data (SIMD) processor, or a VLIW SIMD processor.
19. An integrated circuit comprising:
a data processing engine (DPE) array comprising DPEs, each DPE of the DPEs comprising:
a core;
a memory module including memory, a first memory interface, a second memory interface, direct memory access (DMA) circuitry, hardware lock circuitry, arbitration logic for the memory, and a stall circuit, the first memory interface being directly connected to the core, the second memory interface being directly connected to a core of a neighboring DPE of the DPEs, the hardware lock circuitry coupled to the memory and configured to lock the memory so that the locked memory is accessible only to one of: the core on the DPE or at least one additional core external to the DPE, the arbitration logic coupled to the memory and configured to configured to control which of the first memory interface or second memory interface has access to the memory and further configured to generate a first signal indicating a memory collision in response to detecting the core is attempting to access a same memory bank which the at least one additional core external to the DPE is accessing, and the stall circuit coupled to compute circuitry and configured to provide a stall signal to the compute circuitry, wherein the stall signal is configured to stall the compute circuitry in the core in response to the first signal;
a stream switch connected to the DMA circuitry and the core, the stream switch including one or more configuration registers, the one or more configuration registers being operable to store configuration data to configure the stream switch; and
a memory-mapped switch coupled to the core, the memory module, and the one or more configuration registers of the stream switch, the one or more configuration registers being writeable by one or more transactions via the memory-mapped switch; and
wherein:
the stream switches of the DPEs are coupled together; and
the memory-mapped switches of the DPEs are coupled together.