IP Library Granted Patent US 10,627,673
Granted Patent B2
US 10,627,673 · App. 15/947,575 · Granted Apr 21, 2020

Light emitting diode array containing a multilayer bus electrode and method of making the same

Inventors: Brian Kim (Palisades Park, NJ); Michael Joseph Cich (Fremont, CA); Ansel Saneyuki Reed (Belmont, CA)
Assignee: GLO AB
G02F1/133603G02F1/1343H05B33/0803
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Quick Facts
Patent No.
US 10,627,673
App. No.
15/947,575
Granted
Apr 21, 2020
Kind
B2
Abstract

A light emitting device includes a backplane, an array of light emitting diodes attached to a front side of the backplane, a dielectric matrix layer located on the front side of the backplane and laterally surrounding the array of light emitting diodes, a transparent conductive layer contacting a front side surface of light emitting diodes within the array of light emitting diodes, and a patterned bus electrode layer electrically shorted to the transparent conductive layer and including an array of openings therein. Each light emitting diode within the array of light emitting diodes is located within an area of a respective opening through the patterned bus electrode layer. The patterned bus electrode layer can include at least one light-absorptive electrically conductive layer providing light absorption. Alternatively or additionally, the patterned bus electrode layer can include a reflective metal layer.

Claims (44)

1. A light emitting device comprising:

a backplane;

an array of light emitting diodes attached to a front side of the backplane through an array of solder balls, each solder ball within the array of solder balls being bonded to a device-side bonding pad located on a respective light emitting diode within the array of light emitting diodes and to a respective bond pad located on the backplane;

a dielectric matrix layer located on, and contacting, the front side of the backplane and laterally surrounding the array of light emitting diodes and contacting the array of solder balls;

a transparent conductive layer contacting front side surfaces of the light emitting diodes; and

a patterned bus electrode layer electrically shorted to the transparent conductive layer and including an array of openings therein, wherein each light emitting diode within the array of light emitting diodes is located within an area of a respective opening through the patterned bus electrode layer.

2. The light emitting device of claim 1 , wherein the patterned bus electrode layer comprises at least one light-absorptive electrically conductive layer which provides a higher light absorption than the transparent conductive layer.

3. The light emitting device of claim 2 , wherein the at least one light-absorptive electrically conductive layer comprises at least one metal layer and at least one dielectric material layer that provides higher light absorption of visible light than the at least one metal.

4. The light emitting device of claim 3 , wherein the at least one dielectric material layer comprises a metal oxide material embedded in a resin.

5. The light emitting device of claim 3 , wherein the at least one dielectric material layer comprises a phase matching dielectric layer that induces destructive interference of incoming light along a direction normal to the front surface of the backplane.

6. The light emitting device of claim 2 , wherein the at least one light-absorptive electrically conductive layer comprises a stack of:

a metal layer; and

a light-absorptive layer comprising a material having a higher visible light absorptivity than the metal layer.

7. The light emitting device of claim 6 , wherein the at least one light-absorptive electrically conductive layer is selected from:

a stack of a copper layer and a chromium layer;

a stack of a first chromium layer, a copper layer, and a second chromium layer;

a stack of a gold layer and a chromium layer;

a stack of an aluminum layer and a chromium layer; and

a stack of an aluminum layer and a molybdenum layer.

8. The light emitting device of claim 2 , wherein the at least one light-absorptive electrically conductive layer absorbs more than 90% of visible light.

9. The light emitting device of claim 1 , wherein the patterned bus electrode layer comprises a reflective metal layer reflecting more than 50% of visible light.

10. The light emitting device of claim 9 , wherein the reflective metal layer comprises a planar portion having a uniform thickness and having a top surface that is more proximal to the backplane than top surfaces of the light emitting diodes in the array are to the backplane.

11. The light emitting device of claim 9 , wherein a bottom surface of the transparent conductive layer contacts an array of annular top surfaces of the reflective metal layer.

12. The light emitting device of claim 1 , wherein the patterned bus electrode layer has a higher electrical conductivity than the transparent conductive layer.

13. The light emitting device of claim 1 , wherein the patterned bus electrode layer is located on a front side surface of the transparent conductive layer.

14. The light emitting device of claim 1 , wherein the patterned bus electrode layer is located on a backside surface of the transparent conductive layer.

15. The light emitting device of claim 1 , wherein a top surface of the dielectric matrix layer is coplanar with top surfaces of the light emitting diodes.

16. The light emitting device of claim 1 , wherein:

the transparent conductive layer comprises a material selected from indium tin oxide and aluminum doped zinc oxide; and

the dielectric matrix layer comprises a planarizable dielectric material selected from undoped silicate glass, a doped silicate glass, a flowable oxide (FOX), silicone, and resin.

17. A method of forming a light emitting device, comprising:

bonding an array of light emitting diodes to a front side of a backplane through an array of solder balls, each solder ball within the array of solder balls being bonded to a device-side bonding pad located on a respective light emitting diode within the array of light emitting diodes and to a respective bond pad located on the backplane;

forming a dielectric matrix layer directly on the front side of the backplane around the array of light emitting diodes and directly on the array of solder balls; and

forming a combination of a transparent conductive layer and a patterned bus electrode layer over the dielectric matrix layer,

wherein:

the transparent conductive layer is formed directly on a front side surface of light emitting diodes within the array of light emitting diodes;

the patterned bus electrode layer is electrically shorted to the transparent conductive layer and includes an array of openings therein; and

each light emitting diode within the array of light emitting diodes is located within an area of a respective opening through the patterned bus electrode layer.

18. The method of claim 17 , wherein the patterned bus electrode layer comprises at least one light-absorptive electrically conductive layer providing a higher light absorption than the transparent conductive layer.

19. The method of claim 17 , further comprising planarizing the dielectric matrix layer, wherein a top surface of the dielectric matrix layer is coplanar with top surfaces of the light emitting diodes.

20. The method of claim 17 , wherein:

the transparent conductive layer comprises a material selected from indium tin oxide and aluminum doped zinc oxide;

the dielectric matrix layer comprises a planarizable dielectric material selected from undoped silicate glass, a doped silicate glass, a flowable oxide (FOX), silicone, and resin; and

the dielectric matrix layer is planarized by chemical mechanical planarization.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2024
From: GLO TECHNOLOGIES LLC
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 068297/0220 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 6, 2023
From: SYSONAN, INC.
To: GLO TECHNOLOGIES LLC
Reel/Frame 065178/0210 →
CHANGE OF NAME Recorded Oct 5, 2023
From: NANOSYS, INC.
To: SYSONAN, INC.
Reel/Frame 065156/0416 →
TERMINATION AND RELEASE OF PATENT SECURITY AGREEMENT RECORDED AT REEL 059569 / FRAME 0840 Recorded Sep 7, 2023
From: FORTRESS CREDIT CORP.,
To: NANOSYS, INC.
Reel/Frame 064836/0263 →
SECURITY INTEREST Recorded Apr 1, 2022
From: NANOSYS, INC.
To: FORTRESS CREDIT CORP., AS AGENT
Reel/Frame 059569/0840 →
NUNC PRO TUNC ASSIGNMENT Recorded Aug 13, 2021
From: GLO AB
To: NANOSYS, INC.
Reel/Frame 057184/0564 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2018
From: KIM, BRIAN; CICH, MICHAEL JOSEPH; REED, ANSEL SANEYUKI
To: GLO AB
Reel/Frame 045729/0017 →
Continuity (1)
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