Bias circuit for temperature-compensated varactor
A bias circuit is provided that is configure to control the bias for a diode-connected transistor operating in the sub-threshold region to produce a gate-to-source voltage. A differential tuning voltage derived from the gate-to-source voltage tunes a plurality of varactors.
1. A bias circuit, comprising:
a diode-connected transistor;
a first transistor coupled in series with the diode-connected transistor;
a first output terminal for tuning a varactor, the first output terminal coupled to the source of the diode-connected transistor;
a resistor coupled in series with the diode-connected transistor;
a second output terminal for tuning the varactor, the second output terminal coupled to a first terminal of the resistor; and
a common-mode feedback circuit configured to control an output voltage biasing a gate of the first transistor so that a common-mode voltage for a differential voltage across the first output terminal and the second output terminal equals a reference voltage.
2. The bias circuit of claim 1 , further comprising:
a voltage divider for dividing a power supply voltage to produce the reference voltage, wherein the common-mode feedback circuit is configured to determine an error between the reference voltage and the common-mode voltage for the differential voltage and to control the output voltage responsive to the error.
3. The bias circuit of claim 2 , wherein the common-mode feedback circuit is further configured to receive a bias voltage and to control the output voltage so that it equals the bias voltage when the error is zero.
4. The bias circuit of claim 1 , wherein the varactor comprises a plurality of varactors, and wherein bias circuit is configured so that the differential voltage biases the plurality of varactors.
5. The bias circuit of claim 4 , wherein the plurality of varactors comprises a first set of varactors and a second set of varactors, and wherein the bias circuit is further configured so that the differential voltage is applied across a positive terminal for each varactor in the first set of varactors and a negative terminal for each varactor in the second set of varactors.
6. The bias circuit of claim 1 , wherein the diode-connected transistor is an n-type metal oxide semiconductor (NMOS) transistor.
7. The bias circuit of claim 1 , wherein the diode-connected transistor is an p-type metal oxide semiconductor (PMOS) transistor.
8. The bias circuit of claim 1 , further comprising:
a second transistor arranged in parallel with the diode-connected transistor and the first transistor, the second transistor having a terminal connected to a second terminal for the resistor, wherein a size for the second transistor is greater than a size for the first transistor.
9. The bias circuit of claim 8 , wherein a drain for the diode-connected transistor is connected to the first terminal of the resistor and a source for the diode-connected transistor wherein the second terminal for the diode-connected transistor is connected to a drain of the first transistor.
10. The bias circuit of claim 8 , further comprising a current mirror configured to produce a current that is split between the diode-connected transistor and the second transistor.
11. A method, comprising:
conducting a sub-threshold current through a diode-connected transistor while deriving a differential voltage from a gate-to-source voltage for the diode-connected transistor;
determining an error between a common-mode voltage for the differential voltage and a reference voltage;
adjusting a bias for the diode-connected transistor to reduce the error; and
biasing a plurality of varactors with the differential voltage.
12. The method of claim 11 , wherein conducting the sub-threshold current through the diode-connected transistor comprises
generating a bias current; and
splitting the bias current between the diode-connected transistor and a second transistor so that the second transistor conducts a bulk of the bias current and the diode-connected transistor conducts the sub-threshold current.
13. The method of claim 12 , wherein adjusting the bias for the diode-connected transistor comprises:
adjusting a gate voltage for a third transistor in series with the diode-connected transistor and a gate voltage for the second transistor to reduce the error.
14. The method of claim 11 , further comprising generating the reference voltage by dividing a power supply voltage.
15. The method of claim 11 , wherein the plurality of varactors comprises a first set of varactors and a second set of varactors, and wherein biasing the plurality of varactors with the differential voltage comprises applying the differential voltage across a positive terminal for each varactor in the first set of varactors and a negative terminal for each varactor in the second set of varactors.
16. A bias circuit, comprising:
a diode-connected transistor;
means for driving a sub-threshold current through the diode-connected transistor;
means for producing a differential voltage from a drain-to-source voltage for the diode-connected transistor; and
a common-mode feedback circuit configured to control a bias for the diode-connected transistor so that a common-mode voltage for the differential voltage equals a reference voltage.
17. The bias circuit of claim 16 , wherein the common-mode feedback circuit comprises a switched-capacitor common-mode feedback circuit.
18. The bias circuit of claim 16 , wherein the diode-connected transistor is an n-type metal oxide semiconductor (NMOS) transistor.
19. The bias circuit of claim 16 , wherein the diode-connected transistor is an p-type metal oxide semiconductor (PMOS) transistor.
20. The bias circuit of claim 16 , further comprising means for biasing a plurality of varactors with the differential bias voltage.