Manufacturing method of semiconductor device
View Patent ↗A manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a semiconductor substrate. The barrier layer formed in the first region is thinned before a step of forming a first work function layer on the barrier layer. The first work function layer formed on the first region is then removed. The process of thinning the barrier layer in the first region and the process of removing the first work function layer in the first region are performed separately for ensuring the coverage of the first work function layer in the second region. The electrical performance of the semiconductor device and the uniformity of the electrical performance of the semiconductor device may be improved accordingly.
1. A manufacturing method of a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region adjacent to the first region;
forming a barrier layer on the semiconductor substrate, wherein the barrier layer is formed in the first region and the second region;
performing a first etching process for thinning the barrier layer in the first region, wherein after the first etching process, the barrier layer comprises:
a first part at least partially disposed in the first region and having a first thickness; and
a second part disposed in the second region and having a second thickness, wherein the first thickness is less than the second thickness;
forming a first work function layer on the barrier layer in the first region and the second region after the first etching process; and
performing a second etching process to remove the first work function layer in the first region.
2. The manufacturing method of claim 1 , wherein the first part and the second part of the barrier layer are directly connected with each other, and a step structure is formed at a juncture of the first part and the second part.
3. The manufacturing method of claim 2 , wherein the first work function layer in the second region covers the step structure after the second etching process.
4. The manufacturing method of claim 1 , wherein the first etching process is performed with a first patterned mask layer as a mask, and the barrier layer in the second region is covered by the first patterned mask layer in the first etching process.
5. The manufacturing method of claim 4 , wherein the second etching process is performed with a second patterned mask layer as a mask, and the first work function layer in the second region is covered by the second patterned mask layer in the second etching process.
6. The manufacturing method of claim 5 , wherein first patterned mask layer and the second pattern mask layer are formed by an identical photomask.
7. The manufacturing method of claim 1 , wherein the first etching process and the second etching process comprise a wet etching process respectively.
8. The manufacturing method of claim 7 , wherein an etchant component of the first etching process is identical to an etchant component of the second etching process.
9. The manufacturing method of claim 8 , wherein an etchant concentration of the first etching process is lower than an etchant concentration of the second etching process.
10. The manufacturing method of claim 1 , further comprising:
forming a second work function layer on the first work function layer and the first part of the barrier layer after the second etching process.
11. The manufacturing method of claim 10 , wherein the first work function layer and the second work function layer comprise a P type work function layer and an N type work function layer respectively.
12. The manufacturing method of claim 10 , wherein the first work function layer comprises a single layer structure or a multiple layer structure.
13. The manufacturing method of claim 1 , wherein the barrier layer in the first region is uniformly thinned by the first etching process.
14. The manufacturing method of claim 1 , wherein the barrier layer comprises a metal nitride layer.
15. The manufacturing method of claim 1 , wherein the first region comprises an N type transistor region, the second region comprises a P type transistor region, and the first work function layer comprises a P type work function layer.