On-chip metal-insulator-metal (MIM) capacitor and methods and systems for forming same

1. A method, comprising:

forming a fin in an active region on the semiconductor substrate;

forming an isolation feature on a semiconductor substrate;

forming a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and touching at least one side of the gate electrode, wherein at least one gate of the plurality of gates is on the fin and comprises a gate electrode, and a high-k dielectric layer disposed between the gate electrode and the fin and disposed on and in contact with at least one side of the gate electrode,

forming a spacer touching the high-k dielectric layer on at least one side of the gate electrode of the at least one gate on the fin and touching the high-k dielectric layer on at least one side of each gate electrode of the plurality of gates on the isolation feature; and

depositing a fill metal between the plurality of gates on the isolation feature, wherein the fill metal after deposition touches the high-k dielectric layer on at least one side of and below a top of the gate electrode of at least one of the plurality of gates.

2. The method of claim 1 ; wherein forming the isolation feature comprises forming the isolation feature in an inactive region.

3. The method of claim 1 , further comprising:

forming at least two sources/drains (S/Ds), each S/D disposed on and/or in the fin adjacent to the spacer on each side of the at least one gate;

forming an interlayer dielectric (ILD) over each S/D and between the plurality of gates on the isolation feature, wherein the ILD is disposed in contact with the spacer;

removing the ILD over each S/D and between the plurality of gates on the isolation feature, to yield a plurality of contact trenches each exposing either one of the S/Ds or the isolation feature;

masking the at least one gate and the at least two S/Ds on the fin;

removing the plurality of spacers disposed on and in contact with the high-k dielectric layer on at least one side of each gate electrode of the plurality of gates on the isolation feature;

unmasking the at least one gate and the at least two S/Ds on the fin; and

depositing the fill metal in each contact trench.

4. The method of claim 3 , wherein the plurality of gates on the isolation feature and the at least one gate on the fin are formed in the same process; the ILD over each S/D and the ILD between the plurality of gates on the isolation feature are removed in the same process; and the fill metal between the plurality of gates on the isolation feature and in each contact trench are deposited in the same process.

5. A system, comprising:

a semiconductor device processing system to manufacture a semiconductor device; and

a processing controller operatively coupled to the semiconductor device processing system, the processing controller configured to control an operation of the semiconductor device processing system;

wherein the semiconductor device processing system is adapted to:

form a fin in an active region on the semiconductor substrate;

form an isolation feature on a semiconductor substrate;

form a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and touching at least one side of the gate electrode, wherein at least one gate of the plurality of gates is on the fin and comprises a gate electrode, and a high-k dielectric layer disposed between the gate electrode and the fin and disposed on and in contact with at least one side of the gate electrode;

form a spacer touching the high-k dielectric layer on at least one side of the gate electrode of the at least one gate on the fin and touching the high-k dielectric layer on at least one side of each gate electrode of the plurality of gates on the isolation feature; and

deposit a fill metal between the plurality of gates on the isolation feature, wherein the fill metal after deposition touches the high-k dielectric layer on at least one side of and below a top of the gate electrode of at least one of the plurality of gates.

6. The system of claim 5 , wherein the semiconductor device processing system is adapted to form the fill metal to contact the high-k dielectric layer on the at least one side of the gate electrode.

7. The system of claim 5 , wherein the semiconductor device processing system is further adapted to:

form at least two sources/drains (S/Ds), each S/D disposed on and/or in the fin adjacent to the spacer on each side of the at least one gate;

form an interlayer dielectric (ILD) over each S/D and between the plurality of gates on the isolation feature, wherein the ILD is disposed in contact with the spacer;

remove the ILD over each S/D and between the plurality of gates on the isolation feature, to yield a plurality of contact trenches each exposing either one of the S/Ds or the isolation feature;

mask the at least one gate and the at least two S/Ds on the fin;

remove the plurality of spacers disposed on and in contact with the high-k dielectric layer on at least one side of each gate electrode of the plurality of gates on the isolation feature;

unmask the at least one gate and the at least two S/Ds on the fin; and

deposit the fill metal in each contact trench.

8. The system of claim 7 , wherein the semiconductor device processing system is adapted to form the plurality of gates on the isolation feature and the at least one gate on the fin in the same process; remove the ILD over each S/D and the ILD between the plurality of gates on the isolation feature in the same process; and deposit the fill metal between the plurality of gates on the isolation feature and in each contact trench in the same process.