Self-timed processors implemented with multi-rail null convention logic and unate gates
There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.
1. A self-timed processor comprising:
a plurality of functional blocks comprising multi-rail null convention logic, each of the functional blocks to output one or more multi-rail data values that each alternate between a valid state and a null state, and
a global acknowledge tree to generate a global acknowledge signal provided to all of the plurality of functional blocks, wherein
the global acknowledge signal switches to a first state when all of the one or more multi-rail data values output from all of the plurality of functional blocks are in respective valid states, and
the global acknowledge signal switches to a second state when all of the one or more multi-rail data values output from all of the plurality of functional blocks are in the null state.
2. The self-timed processor of claim 1 , wherein each of the plurality of functional blocks further comprises:
a register to output an acknowledge signal to the global acknowledge tree; and
combinatorial logic to output the one or more multi-rail data values to the register,
wherein the combinatorial logic of at least one of the plurality of functional blocks comprises one or more non-threshold, unate gates.
3. The self-timed processor of claim 2 , wherein
the combinatorial logic of all of the plurality of functional blocks comprises one or more unate gates, which do not provide input completeness.
4. The self-timed processor of claim 3 , wherein
the combinatorial logic of all of the plurality of functional blocks does not include threshold gates.
5. The self-timed processor of claim 4 , wherein
the registers included in the plurality of functional blocks comprise threshold gates.
6. The self-timed processor of claim 1 , wherein
the global acknowledge tree comprises gates that are only threshold gates, and which provide input completeness.
7. The self-timed processor of claim 1 , wherein
at least some of the plurality of functional blocks are arranged as a pipeline.
8. The self-timed processor of claim 1 , wherein
at least one of the plurality of functional blocks receives data from a source external to the self-timed processor, and
the global acknowledge signal is provided to the source.
9. The self-timed processor of claim 1 , wherein
at least one of the plurality of functional blocks sends data to a destination external to the self-timed processor, and
the global acknowledge signal is provided to the destination.
10. The self-timed processor of claim 1 , wherein
at least one of the plurality of registers sends data to a destination external to the self-timed processor, and
the global acknowledge signal is provided to the destination.
11. The self-timed processor of claim 1 , wherein
the global acknowledge signal switches to a first state to signal the functional blocks to enter a null phase when all of the one or more multi-rail data values output from all of the plurality of functional blocks are in respective valid states, and
the global acknowledge signal switches to a second state to signal the functional blocks to enter a data phase when all of the one or more multi-rail data values output from all of the plurality of functional blocks are in a null state.
12. A self-timed processor comprising:
a plurality of registers; and
a global acknowledge tree to generate a global acknowledge signal provided to all of the plurality of registers, wherein
two or more multi-rail null convention logic (NCL) data values output from a first one or more of the plurality of registers are combined by one or more unate gates to provide at least one multi-rail NCL input to a second one of the plurality of registers, wherein the two or more multi-rail NCL data values each alternate between a valid state and a null state, and
the global acknowledge signal switches to a first state when all of the two or more multi-rail NCL data values output from all of the plurality of registers are in respective valid states, and
the global acknowledge signal switches to a second state when all of the two or more NCL multi-rail values data output from all of the plurality of registers are in the null state.
13. The self-timed processor of claim 12 , wherein at least some of the plurality of registers comprise threshold gates.
14. The self-timed processor of claim 12 , wherein
the global acknowledge tree comprises gates that are only threshold gates, and which provide input completeness.
15. The self-timed processor of claim 12 , wherein
at least one of the plurality of registers receives data from a source external to the self-timed processor, and
the global acknowledge signal is provided to the source.
16. The self-timed processor of claim 12 , wherein
the global acknowledge signal switches to a first state to signal the functional blocks to enter a null phase when all of the two or more multi-rail NCL data values output from all of the plurality of registers are in respective valid states, and
the global acknowledge signal switches to a second state to signal the functional blocks to enter a data phase when all of the one or more multi-rail NCL data values output from all of the plurality of registers are in a null state.
17. A method of processing data within a self-timed processor, comprising:
combining two or more multi-rail null convention logic (NCL) data values output from a first one or more of a plurality of registers using one or more unate gates to provide at least one multi-rail NCL input to a second one of the plurality of registers, wherein the two or more multi-rail NCL data values each alternate between a valid state and a null state, and
generating a global acknowledge signal provided to all of the plurality of registers, wherein
the global acknowledge signal switches to a first state when all of the two or more multi-rail NCL data values output from all of the plurality of registers are in respective valid states, and
the global acknowledge signal switches to a second state when all of the two or more NCL multi-rail values data output from all of the plurality of registers are in the null state.
18. The method of claim 17 , wherein
generating the global acknowledge signal is performed by an acknowledge tree comprising gates that are only threshold gates, and which provide input completeness.
19. The method of claim 17 , further comprising:
receiving data from a source external to the self-timed processor, and
providing the global acknowledge signal to the source.
20. The method of claim 17 , further comprising:
providing data to a destination external to the self-timed processor, and
providing the global acknowledge signal to the destination,
providing the global acknowledge signal to the source.