Method for fabricating contact electrical fuse
A method for fabricating semiconductor device includes the steps of first forming a first dielectric layer on a substrate, in which a first conductor is embedded within the first dielectric layer. Next, a second dielectric layer is formed on the first dielectric layer, part of the second dielectric layer is removed to form a contact hole, and a lateral etching process is conducted to expand the contact hole to form a funnel-shaped opening. Next, a metal layer is formed in the funnel-shaped opening, and the metal layer is planarized to form a second conductor.
1. A method for fabricating semiconductor device, comprising:
providing a substrate;
forming a second dielectric layer on the substrate;
forming a first conductor in the second dielectric layer;
forming a stop layer on the first conductor and the second dielectric layer;
forming a first dielectric layer on the stop layer;
forming a via hole in the first dielectric layer and the stop layer to expose the first conductor;
performing a lateral etching process to expand the via hole for forming a funnel-shaped opening after exposing the first conductor, wherein an etching gas used to perform the lateral etching process comprises nitrogen and helium;
forming a metal layer in the funnel-shaped opening; and
planarizing the metal layer for forming a second conductor, wherein the second conductor comprises a first portion comprising a first sidewall, and a second portion in embedded in the first dielectric layer, wherein the second portion comprises a second sidewall and a third sidewall, each of the second sidewall and the third sidewall is planar, and wherein a first angle at an intersection of the first sidewall and a horizontal plane is between 80 degrees to 90 degrees, and wherein a second angle at the intersection of the second sidewall and a horizontal plane is between 30 degrees to 50 degrees, and wherein a third angle at the intersection of the third sidewall and a horizontal plane is between 85 degrees to 90 degrees.
2. The method of claim 1 , wherein a top surface of the first conductor and a top surface of the second dielectric layer are coplanar.
3. The method of claim 1 , further comprising:
forming a first mask layer on the first dielectric layer;
performing a first etching process to pattern the first mask layer for forming a patterned first mask layer;
forming a second mask layer on the patterned first mask layer; and
performing a second etching process to form the via hole in the second mask layer and the first dielectric layer.
4. The method of claim 3 , further comprising using a chlorine-containing gas to perform the first etching process.
5. The method of claim 3 , further comprising using a fluorine-containing gas to perform the second etching process.
6. The method of claim 1 , wherein the second conductor is funnel-shaped.
7. The method of claim 6 , wherein the second conductor comprises a first slope and a second slope, wherein the first slope is different from the second slope.
8. The method of claim 1 , wherein a radio frequency (RF) power used during the lateral etching process is between 1000 W to 2000 W.