Electrostatic discharge protection circuit
The present application belongs to field of integrated circuit and discloses an electrostatic discharge protection circuit comprising a first N-type transistor and a second N-type transistor. The first N-type transistor comprises a first gate terminal coupled to a ground terminal; a first electrode terminal coupled to the first gate terminal; and a second electrode terminal. The second N-type transistor comprises a second gate terminal coupled to a metal pad; a third electrode terminal coupled to the second gate terminal; a fourth electrode terminal, coupled to the second electrode terminal; and a first deep N well, disposed under the third electrode terminal and the fourth electrode terminal. The ESD protection circuits provided by the embodiments of the present application have advantages of small circuit area and good ESD protection.
1. An electrostatic discharge (ESD) protection circuit, comprising:
a first N-type transistor, comprising:
a first gate terminal, coupled to a ground terminal;
a first electrode terminal, coupled to the first gate terminal; and
a second electrode terminal; and
a second N-type transistor, comprising:
a second gate terminal, coupled to a metal pad;
a third electrode terminal, coupled to the second gate terminal;
a fourth electrode terminal, coupled to the second electrode terminal;
a first deep N well, disposed under the third electrode terminal and the fourth electrode terminal;
a first P-well, disposed between the third electrode terminal, the fourth electrode terminal and the first deep N-well, wherein the second gate terminal, the third electrode terminal and the fourth electrode terminal are disposed on the first P-well;
a first N-well, wherein the first N-well is disposed by a side of the first P-well; and
a first N-type region, wherein the first N-type region is disposed in the first N-well, and the first N-type region is coupled to a voltage supplying circuit which provides a supply voltage.
2. The ESD protection circuit as claim 1 , wherein the first N-type transistor further comprises:
a first base terminal, coupled to the first electrode terminal.
3. The ESD protection circuit as claim 1 , further comprising:
a diode, coupled to the second N-type transistor.
4. The ESD protection circuit as claim 3 , wherein the diode comprises:
a first terminal, coupled to the second N-type transistor; and
a second terminal, configured to receive the supply voltage.
5. The ESD protection circuit as claim 4 , wherein the diode further comprises:
a second N-well, disposed under the first terminal and the second terminal.
6. The ESD protection circuit as claim 4 , wherein the diode further comprises:
a second P-well, disposed under the first terminal and the second terminal.
7. The ESD protection circuit as claim 6 , wherein the diode further comprises:
a second deep N-well, disposed under the second P-well.
8. The ESD protection circuit as claim 1 , further comprising:
a plurality of diodes, formed as a diode series;
wherein an end of the diode series is coupled to the second N-type transistor, the other end of the diode series is configured to receive the supply voltage.
9. The ESD protection circuit as claim 1 , wherein a first current flows to the ground terminal through the first N-type transistor in response to a voltage of the metal pad being a positive ESD voltage.
10. The ESD protection circuit as claim 1 , wherein the first N-type transistor is formed as a first bipolar transistor in response to a voltage of the metal pad being a positive ESD voltage.
11. The ESD protection circuit as claim 9 , wherein the positive ESD voltage is larger than 1 kilovolt.
12. The ESD protection circuit as claim 1 , wherein a second current flows to the metal pad through the second N-type transistor in response to a voltage of the metal pad being a negative ESD voltage.
13. The ESD protection circuit as claim 1 , wherein the second N-type transistor is formed as a second bipolar transistor in response to a voltage of the metal pad being a negative ESD voltage.
14. The ESD protection circuit as claim 12 , wherein the negative ESD voltage is less than negative 1 kilovolt.