Memory system and operating method thereof

1. A memory system comprising:

an ECC unit suitable for generating a second data error flag and a second DBI error flag based on second data, a second DBI flag, and a second parity, which are provided through a channel, and generating error-corrected third data and an error-corrected third DBI flag based on the second data error flag and the second DBI error flag;

a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits substituting the third DBI flag are inverted, based on the third data and the third DBI flag; and

a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

2. The memory system of claim 1 , wherein the DM unit comprises a first DM sub unit and a second DM sub unit,

the second data includes a plurality of second data groups, and

the first DM sub unit generates:

a first pre-DM flag indicating whether the number of high logics of a plurality of bits included in each of the second data groups is at a boundary of a masking value; and

a second pre-DM flag indicating whether the number of high logics of the plurality of bits included in each of the second data groups is equal to or greater than the masking value.

3. The memory system of claim 2 , wherein the second DM sub unit generates the DM flag bit based on the first pre-DM flag, the second pre-DM flag, the second data, and the second data error flag.

4. The memory system of claim 3 , wherein the second DM sub unit generates:

the DM flag bit by determining whether the second pre-DM flag is corrected, based on the second data and the second data error flag, when the first pre-DM flag is high logic; and

the DM flag bit having the same logic as that of the second pre-DM flag when the first pre-DM flag is low logic.

5. The memory system of claim 4 , wherein, when the first pre-DM flag is high logic, the second DM sub unit generates the DM flag bit having the same logic as that of the second pre-DM flag if an error does not exist in the plurality of bits constituting the second data group corresponding to the first pre-DM flag.

6. The memory system of claim 4 , wherein, when the first pre-DM flag is high logic and the second pre-DM flag is low logic, the second DM sub unit generates the DM flag bit of low logic if a bit in which an error occurs among the plurality of bits included in the second data group is high logic.

7. The memory system of claim 4 , wherein, when the first pre-DM flag is high logic and the second pre-DM flag is low logic, the second DM sub unit generates the DM flag bit of high logic if a bit in which an error occurs among the plurality of bits included in the second data group is low logic.

8. The memory system of claim 4 , wherein, when the first pre-DM flag is high logic and the second pre-DM flag is high logic, the second DM sub unit generates the DM flag bit of low logic if a bit in which an error occurs among the plurality of bits included in the second data group is high logic.

9. The memory system of claim 4 , wherein, when the first pre-DM flag is high logic and the second pre-DM flag is high logic, the second DM sub unit generates the DM flag bit of high logic if a bit in which an error occurs among the plurality of bits included in the second data group is low logic.

10. The memory system of claim 9 , wherein the fourth data includes a plurality of fourth data groups,

the fourth data group corresponding to the DM flag bit of high logic is a data group on which the write operation is not performed, and

the fourth data group corresponding to the DM flag bit of low logic is a data group on which the write operation is performed.

11. A method of operating a memory system, the method comprising:

generating a second data error flag and a second DBI error flag based on second data, a second DBI flag, and a second parity, which are provided through a channel, and generating error-corrected third data and an error-corrected third DBI flag based on the second data error flag and the second DBI error flag;

generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and

generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

12. The method of claim 11 , wherein the generating of the DM flag comprises a first DM sub process and a second DM sub process,

the second data includes a plurality of second data groups, and

the first DM sub process comprises generating:

a first pre-DM flag indicating whether the number of high logics of a plurality of bits included in each of the second data groups is at a boundary of a masking value; and

a second pre-DM flag indicating whether the number of high logics of the plurality of bits included in each of the second data groups is equal to or greater than the masking value.

13. The method of claim 12 , wherein the second DM sub process comprises generating the DM flag bit based on the first pre-DM flag, the second pre-DM flag, the second data, and the second data error flag.

14. The method of claim 13 , wherein the second DM sub process comprises:

generating the DM flag bit by determining whether the second pre-DM flag is corrected, based on the second data and the second data error flag, when the first pre-DM flag is high logic; and

generating the DM flag bit having the same logic as that of the second pre-DM flag when the first pre-DM flag is low logic.

15. The method of claim 14 , wherein, when the first pre-DM flag is high logic, the second DM sub process comprises generating the DM flag bit having the same logic as that of the second pre-DM flag if an error does not exist in the plurality of bits constituting the second data group corresponding to the first pre-DM flag.

16. The method of claim 14 , wherein, when the first pre-DM flag is high logic and the second pre-DM flag is low logic, the second DM sub process comprises generating the DM flag bit of low logic if a bit in which an error occurs among the plurality of bits included in the second data group is high logic.

17. The method of claim 14 , wherein, when the first pre-DM flag is high logic and the second pre-DM flag is low logic, the second DM sub process comprises generating the DM flag bit of high logic if a bit in which an error occurs among the plurality of bits included in the second data group is low logic.

18. The method of claim 14 , wherein, when the first pre-DM flag is high logic and the second pre-DM flag is high logic, the second DM sub process comprises generating the DM flag bit of low logic if a bit in which an error occurs among the plurality of bits included in the second data group is high logic.

19. The method of claim 14 , wherein, when the first pre-DM flag is high logic and the second pre-DM flag is high logic, the second DM sub process comprises generating the DM flag bit of high logic if a bit in which an error occurs among the plurality of bits included in the second data group is low logic.

20. The method of claim 19 , wherein the fourth data includes a plurality of fourth data groups, and

the method further comprises:

not performing the write operation on the fourth data group corresponding to the DM flag bit of high logic; and

performing the write operation on the fourth data group corresponding to the DM flag bit of low logic.