Circuits with low-pass filters and differential amplifiers

1. A circuit comprising:

a first set of serially-connected inverters comprising an input port, the first set of serially-connected inverters comprising a first subset of serially-connected inverters, the first subset of serially-connected inverters odd in number and comprising an input port and an output port;

a first low-pass filter comprising an input port coupled to the output port of the first subset of serially-connected inverters, and an output port;

a second low-pass filter comprising an input port coupled to the input port of the first subset of serially-connected inverters, and an output port; and

a first differential amplifier comprising a first input port coupled to output port of the first low-pass filter, a second input port coupled to the output port of the second low-pass filter, and an output port coupled to the input port of the first set of serially-connected inverters;

the first differential amplifier comprising a capacitor, the capacitor of the first differential amplifier comprising a first terminal coupled to the first input port of the first differential amplifier and a second terminal coupled to the output port of the first differential amplifier.

2. The circuit of claim 1 , further comprising:

a first clock signal input port; and

a first coupling capacitor comprising a first terminal coupled to the first clock signal input port, and a second terminal coupled to the input port of the first set of serially-connected inverters.

3. The circuit of claim 1 , further comprising:

a first resistor comprising a first terminal coupled to the output port of the first differential amplifier, and a second terminal coupled to the input port of the first set of serially-connected inverters.

4. The circuit of claim 3 , further comprising:

a first clock signal input port; and

a first coupling capacitor comprising a first terminal coupled to the first clock signal input port, and a second terminal coupled to the input port of the first set of serially-connected inverters.

5. The circuit of claim 4 , further comprising:

a second set of serially-connected inverters comprising an input port, the second set of serially-connected inverters comprising a second subset of serially-connected inverters, the second subset of serially-connected inverters odd in number and comprising an input port and an output port;

a third low-pass filter comprising an input port coupled to the output port of the second subset of serially-connected inverters, and an output port;

a fourth low-pass filter comprising an input port coupled to the input port of the second subset of serially-connected inverters, and an output port;

a second differential amplifier comprising a first input port coupled to output port of the third low-pass filter, a second input port coupled to the output port of the fourth low-pass filter, and an output port coupled to the input port of the second set of serially-connected inverters;

a second clock signal input port; and

a second coupling capacitor comprising a first terminal coupled to the second clock signal input port, and a second terminal coupled to the input port of the second set of serially-connected inverters.

6. A circuit comprising:

a first set of serially-connected inverters comprising an input port, the first set of serially-connected inverters comprising a first subset of serially-connected inverters, the first subset of serially-connected inverters odd in number and comprising an input port and an output port;

a first low-pass filter comprising an input port coupled to the output port of the first subset of serially-connected inverters, and an output port;

a second low-pass filter comprising an input port coupled to the input port of the first subset of serially-connected inverters, and an output port; and

a first differential amplifier comprising a first input port coupled to output port of the first low-pass filter, a second input port coupled to the output port of the second low-pass filter, and an output port coupled to the input port of the first set of serially-connected inverters;

the first set of serially-connected inverters comprising:

a first inverter comprising an input port coupled to the input port of the first set of serially-connected inverters, and an output port;

a second inverter comprising an input port coupled to the output port of the first inverter, and an output port;

a third inverter comprising an input port coupled to the output port of the second inverter, and an output port; and

a fourth inverter comprising an input port coupled to the output port of the third inverter, and an output port;

wherein the first subset of serially-connected inventors comprises the third inverter;

a first switch to couple the input port of the second low-pass filter to the output port of the second inverter;

a second switch to couple the input port of the second low-pass filter to the output port of the fourth inverter;

a first clock signal input port;

a second clock signal input port;

a fifth inverter comprising an input port coupled to the second clock signal input port, and an output port;

a first pair of cross-coupled inverters coupled to the output port of the first inverter and to the output port of the fifth inverter;

a sixth inverter comprising an input port coupled to the output port of the fifth inverter, and an output port;

a second pair of cross-coupled inverters coupled to the output port of the second inverter and to the output port of the sixth inverter;

a seventh inverter comprising an input port coupled to the output port of the sixth inverter, and an output port;

a third pair of cross-coupled inverters coupled to the output port of the third inverter and to the output port of the seventh inverter;

a third low-pass filter comprising an input port coupled to the output port of the seventh inverter, and an output port;

a fourth low-pass filter comprising an input port coupled to the output port of the sixth inverter, and an output port; and

a second differential amplifier comprising a first input port coupled to output port of the third low-pass filter, a second input port coupled to the output port of the fourth low-pass filter, and an output port coupled to the input port of the fifth inverter.

7. The circuit of claim 6 , further comprising a third switch to couple the input port of the fourth low-pass filter to the output port of the sixth inverter.

8. The circuit of claim 7 , further comprising:

an eighth inverter comprising an input port coupled to the output port of the seventh inverter, and an output port; and

a fourth switch to couple the input port of the fourth low-pass filter to the output port of the eighth inverter.

9. The circuit of claim 8 , further comprising:

a first coupling capacitor comprising a first terminal coupled to the first clock signal input port, and a second terminal coupled to the input port of the first inverter; and

a second coupling capacitor comprising a first terminal coupled to the second clock signal input port, and a second terminal coupled to the input port of the fifth inverter.

10. The circuit of claim 9 , further comprising:

a first resistor comprising a first terminal coupled to the output port of the first differential amplifier, and a second terminal coupled to the input port of the first inverter; and

a second resistor comprising a first terminal coupled to the output port of the second differential amplifier, and a second terminal coupled to the input port of the fifth inverter.

11. The circuit of claim 10 ,

the first differential amplifier comprising a capacitor, the capacitor of the first differential amplifier comprising a first terminal coupled to the first input port of the first differential amplifier and a second terminal coupled to the output port of the first differential amplifier; and

the second differential amplifier comprising a capacitor, the capacitor of the second differential amplifier comprising a first terminal coupled to the first input port of the second differential amplifier and a second terminal coupled to the output port of the second differential amplifier.