Power semiconductor device
View Patent ↗A power semiconductor device includes a substrate including a first epitaxial layer, a second epitaxial layer, and a base substrate where the first epitaxial layer is disposed between the second epitaxial layer and the base substrate. The power semiconductor device includes an anode electrode and a cathode electrode disposed on the substrate, a well region disposed inside the substrate in a lower portion of the anode electrode, and having p-type conductivity. The power semiconductor device includes an NISO region disposed in a lower portion of the well region inside the substrate, and having a first n-type impurity concentration. The power semiconductor device includes an n-type buried layer disposed in a lower portion of the NISO region, and having a second impurity concentration greater than the first n-type impurity concentration, inside the substrate.
1. A power semiconductor device comprising:
a substrate including:
a first epitaxial layer,
a second epitaxial layer, and
a base substrate, the first epitaxial layer being disposed between the second epitaxial layer and the base substrate;
an anode electrode;
a cathode electrode;
a well region disposed inside the substrate below the anode electrode, and having p-type conductivity;
an NISO region disposed below the well region, and having a first n-type impurity concentration, inside the substrate; and
an n-type buried layer disposed below the NISO region, and having a second n-type impurity concentration greater than the first n-type impurity concentration, inside the substrate.
2. The power semiconductor device of claim 1 , wherein the well region and the NISO region define a p-n junction diode.
3. The power semiconductor device of claim 1 , wherein the n-type buried layer is below substantially the entirety of the NISO region.
4. The power semiconductor device of claim 1 , wherein at least a portion of a bottom surface of the NISO region is in contact with an upper surface of the n-type buried layer.
5. The power semiconductor device of claim 1 , further comprising an n-type barrier layer disposed on a side of the NISO region, inside the substrate.
6. The power semiconductor device of claim 5 , wherein the n-type barrier layer is disposed on the n-type buried layer.
7. The power semiconductor device of claim 5 , wherein at least a portion of a bottom surface of the n-type barrier layer is in contact with an upper surface of the n-type buried layer.
8. The power semiconductor device of claim 5 , wherein the n-type barrier layer has a third n-type impurity concentration greater than the first n-type impurity concentration.
9. The power semiconductor device of claim 5 , further comprising an n-type sink disposed on the n-type barrier layer, inside the substrate, the n-type sink having a third n-type impurity concentration greater than the first n-type impurity concentration.
10. The power semiconductor device of claim 5 , further comprising an element isolation region disposed on one side of the NISO region, inside the substrate, the element isolation region including an upper element isolation layer and a lower element isolation layer disposed below the upper element isolation layer.
11. The power semiconductor device of claim 10 , wherein a bottom surface of the lower element isolation layer is located at a higher level than a bottom surface of the n-type buried layer.
12. A power semiconductor device, comprising:
a base substrate;
a first epitaxial layer disposed on the base substrate;
a second epitaxial layer disposed on the first epitaxial layer;
an anode electrode and a cathode electrode disposed on the second epitaxial layer;
a p-type well region disposed below the anode electrode inside the second epitaxial layer;
an NISO region disposed below the p-type well region, and in which at least a portion is located inside the first epitaxial layer; and
an n-type buried layer disposed below the NISO region, and in which at least a portion is located inside the base substrate.
13. The power semiconductor device of claim 12 , wherein the NISO region has a first n-type impurity concentration, and the n-type buried layer has a second n-type impurity concentration greater than the first n-type impurity concentration.
14. The power semiconductor device of claim 12 , further comprising an n-type barrier layer disposed on one side of the NISO region and disposed on the n-type buried layer.
15. The power semiconductor device of claim 14 , wherein the NISO region has a first n-type impurity concentration, and the n-type barrier layer has a second n-type impurity concentration greater than the first n-type impurity concentration.
16. The power semiconductor device of claim 12 , further comprising an element isolation region disposed on one side of the NISO region, wherein the element isolation region includes a lower element isolation layer in which at least a portion is located inside the first epitaxial layer, and an upper element isolation layer in which at least a portion is located inside the second epitaxial layer, and on the lower element isolation layer.
17. A power semiconductor device, comprising:
a substrate including:
a first epitaxial layer,
a second epitaxial layer, and
a base substrate, the first epitaxial layer being disposed between the second epitaxial layer and the base substrate; and
a plurality of unit cells disposed on the substrate, each of the plurality of unit cells including:
an anode electrode and a cathode electrode disposed at a distance away from each other on the substrate,
a well region disposed inside the substrate below the anode electrode, and having a p-type conductivity, and
an NISO region disposed below the well region, and having a first n-type impurity concentration inside the substrate; and
an n-type buried layer disposed below the NISO region of each of the plurality of unit cells, and having a second n-type impurity concentration greater than the first n-type impurity concentration inside the substrate.
18. The power semiconductor device of claim 17 , wherein the cathode electrode inside one unit cell among the plurality of unit cells is connected to the cathode electrode inside a unit cell adjacent thereto.
19. The power semiconductor device of claim 17 , wherein the n-type buried layer is disposed to be overlapped with substantially the entire area of the plurality of unit cells.
20. The power semiconductor device of claim 17 , wherein each of the plurality of unit cells further includes an n-type barrier layer disposed on both sides of the NISO region on the n-type buried layer.