Semiconductor device and method of forming the same
A semiconductor device includes a substrate, wherein the substrate includes a channel region. The semiconductor device further includes an isolation feature in the substrate. The isolation feature includes a first portion in the substrate, and a second portion extending along a top surface of the substrate. The second portion partially covers the channel region. The semiconductor device further includes a gate structure over the substrate, wherein the gate structure partially covers the second portion of the isolation feature.
1. A semiconductor device comprising:
a substrate, wherein the substrate includes a channel region;
an isolation feature in the substrate, wherein the isolation feature comprises:
a first portion in the substrate, and
a second portion extending along a top surface of the substrate, wherein the second portion partially covers the channel region; and
a gate structure over the substrate, wherein the gate structure partially covers the second portion of the isolation feature, the gate structure covers less than all of the second portion of the isolation feature, and the gate structure covers an entirety of the channel region.
2. The semiconductor device of claim 1 , wherein a length of the channel region covered by the second portion is greater than about 5 nanometers (nm).
3. The semiconductor device of claim 1 , wherein the channel region directly contacts the first portion.
4. The semiconductor device of claim 1 , wherein the gate structure comprises a gate electrode, and a thickness of the gate electrode over the second portion is less than a thickness of the gate electrode over a portion of the channel region exposed by the second portion.
5. The semiconductor device of claim 1 , wherein the gate structure comprises a dielectric layer, and the dielectric layer extends over the second portion.
6. The semiconductor device of claim 1 , wherein the first portion is integral with the second portion.
7. The semiconductor device of claim 1 , further comprising an implant contact in the substrate, wherein the first portion is between the implant contact and the channel region.
8. The semiconductor device of claim 1 , further comprising an implant region between the first portion and the channel region.
9. The semiconductor device of claim 8 , further comprising an implant contact in the substrate, wherein the first portion is between the implant contact and the channel region.
10. A semiconductor device comprising:
a substrate, wherein the substrate includes a channel region;
an isolation feature in the substrate, wherein the isolation feature comprises:
a first portion in the substrate,
a second portion extending along a top surface of the substrate, wherein the second portion partially covers the channel region, and
a third portion extending along the top surface of the substrate, wherein the third portion partially covers a region of the substrate on an opposite side of the isolation feature from the channel region, and the region of the substrate is separated from the channel region by the first portion of the isolation feature; and
a gate structure over the substrate, wherein the gate structure partially covers the second portion of the isolation feature, and the gate structure covers less than all of the second portion of the isolation feature.
11. The semiconductor device of claim 10 , wherein a depth of the first portion from the top surface of the substrate is greater than a depth of the channel region from the top surface of the substrate.
12. The semiconductor device of claim 10 , further comprising an implant contact in the substrate, wherein the third portion partially covers the implant contact.
13. The semiconductor device of claim 10 , wherein the channel region directly contacts the first portion.
14. The semiconductor device of claim 10 , further comprising an implant region between the channel region and the first portion.
15. A semiconductor device comprising:
a substrate, wherein the substrate includes a channel region;
an isolation feature in the substrate, wherein the isolation feature comprises:
a first portion in the substrate, and
a second portion extending along a top surface of the substrate, wherein a bottom surface of the second portion is below the top surface of the substrate; and
a gate structure over the substrate, wherein the gate structure is over the second portion of the isolation feature.
16. The semiconductor device of claim 15 , wherein the isolation feature further comprises a third portion extending along the top surface of the substrate, and the third portion is on an opposite side of the first portion from the second portion.
17. The semiconductor device of claim 15 , further comprising an implant region in the substrate, wherein the implant region contacts a sidewall of the first portion.
18. The semiconductor device of claim 15 , further comprising a contact area in the substrate, wherein the contact area is on an opposite side of the first portion from the channel region.
19. The semiconductor device of claim 18 , wherein the isolation feature further comprises a third portion extending along a top surface of the contact area, and the third portion is on an opposite side of the first portion from the second portion.
20. The semiconductor device of claim 15 , wherein the gate structure covers an entirety of the second portion that is over the channel region.