SEMICONDUCTOR DEVICE AND METHOD OF INTEGRATING POWER MODULE WITH INTERPOSER AND OPPOSING SUBSTRATES
A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.
1 . A semiconductor device, comprising:
a substrate;
a plurality of first interconnect pads formed over a surface of the substrate; and
a plurality of second interconnect pads formed over the surface of the substrate, wherein the second interconnect pads have an area different from an area of the first interconnect pads, and the first interconnect pads and second interconnect pads are electrically common and arranged in an identifiable pattern for alignment.
2 . The semiconductor device of claim 1 , wherein the identifiable pattern includes rows of the first interconnect pads.
3 . The semiconductor device of claim 1 , wherein the identifiable pattern includes alternating offset ones of the first interconnect pads.
4 . The semiconductor device of claim 1 , wherein the identifiable pattern includes the first interconnect pads interposed between the second interconnect pads.
5 . The semiconductor device of claim 1 , further including a transistor formed within the substrate.
6 . The semiconductor device of claim 1 , further includes a plurality of bumps formed over the first interconnect pads and second interconnect pads.
7 . A semiconductor device, comprising:
a substrate; and
a plurality of interconnect pads formed in an identifiable pattern over a surface of the substrate, wherein first ones of the interconnect pads have an area different from an area of second ones of the interconnect pads.
8 . The semiconductor device of claim 7 , wherein the interconnect pads are electrically common.
9 . The semiconductor device of claim 7 , wherein the identifiable pattern includes rows of the interconnect pads.
10 . The semiconductor device of claim 7 , wherein the identifiable pattern includes alternating offset ones of the interconnect pads.
11 . The semiconductor device of claim 7 , wherein the identifiable pattern includes the first ones of the interconnect pads interposed between the second ones of the interconnect pads.
12 . The semiconductor device of claim 7 , further including a transistor formed within the substrate.
13 . The semiconductor device of claim 7 , further includes a plurality of bumps formed over the interconnect pads.
14 . A method of making a semiconductor device, comprising:
providing a substrate;
forming a plurality of first interconnect pads over a surface of the substrate; and
forming a plurality of second interconnect pads over the surface of the substrate, wherein the second interconnect pads have an area different from an area of the first interconnect pads, and the first interconnect pads and second interconnect pads are arranged in an identifiable pattern.
15 . The method of claim 14 , wherein the first interconnect pads and second interconnect pads are electrically common.
16 . The method of claim 14 , wherein the identifiable pattern includes rows of the first interconnect pads.
17 . The method of claim 14 , wherein the identifiable pattern includes alternating offset ones of the first interconnect pads.
18 . The method of claim 14 , wherein the identifiable pattern includes the first interconnect pads interposed between the second interconnect pads.
19 . The method of claim 14 , further including forming a transistor within the substrate.
20 . The method of claim 14 , further includes forming a plurality of bumps over the first interconnect pads and second interconnect pads.