Semiconductor die singulation methods
View Patent ↗Methods of singulating semiconductor die. Specific implementations may include: providing a semiconductor wafer including a plurality of die located on a first side of the semiconductor wafer where the plurality of die include a desired thickness. The method may include etching a plurality of trenches into the semiconductor wafer from the first side of the semiconductor wafer where the plurality of trenches is located adjacent to a perimeter of the plurality of die. A depth of the plurality of trenches may be greater than the desired thickness of the plurality of die. The method may also include mounting the first side of the semiconductor wafer to a tape, thinning a second side of the semiconductor wafer, exposing the plurality of trenches while thinning the second side, and singulating the plurality of die through exposing the plurality of trenches.
1. A method of singulating a plurality of die, the method comprising:
providing a semiconductor wafer comprising a plurality of die located on a first side of the semiconductor wafer, the plurality of die comprising a desired thickness;
etching a plurality of trenches into the semiconductor wafer from the first side of the semiconductor wafer, the plurality of trenches located adjacent a perimeter of the plurality of die and a depth of the plurality of trenches being greater than the desired thickness of the plurality of die;
mounting the first side of the semiconductor wafer to a back grinding tape;
thinning a second side of the semiconductor wafer to a predetermined distance between the second side of the semiconductor wafer and the depth of the plurality of trenches;
from the first side of the semiconductor wafer, etching through the predetermined distance between the second side of the semiconductor wafer and the depth of the plurality of trenches to singulate the plurality of die.
2. The method of claim 1 , wherein etching the plurality of trenches comprises plasma etching.
3. The method of claim 1 , wherein etching the plurality of trenches further comprises defining a pattern of the plurality of trenches using one of passivation material, metal material, photolithographic masking, temporary film, shadow masking, and any combination thereof.
4. The method of claim 1 , wherein the semiconductor wafer comprises silicon and etching the plurality of trenches and etching through the predetermined distance both further comprise using a Bosch deep reactive ion etch (DRIE) process.
5. The method of claim 1 , further comprising one of the following after etching the plurality of trenches:
forming a plurality of bumps on the plurality of die;
testing one or more of the plurality of die;
probing one or more of the plurality of die;
adding memory data to one or more of the plurality of die;
forming a solderable surface on a surface of one or more of the plurality of die; and
any combination thereof.
6. The method of claim 1 , wherein thinning the second side of the semiconductor wafer to the predetermined distance further comprises using a Taiko grinding process.
7. The method of claim 1 , further comprising picking the plurality of die from the back grinding tape.
8. A method of singulating a plurality of die, the method comprising:
providing a semiconductor wafer comprising a plurality of die located on a first side of the semiconductor wafer, the plurality of die comprising a desired thickness;
etching a plurality of trenches into the semiconductor wafer from the first side of the semiconductor wafer, the plurality of trenches located adjacent a perimeter of the plurality of die and a depth of the plurality of trenches being greater than the desired thickness of the plurality of die;
mounting the first side of the semiconductor wafer to a back grinding tape;
thinning a second side of the semiconductor wafer to a predetermined distance between the second side of the semiconductor wafer and the depth of the plurality of trenches;
demounting the first side of the semiconductor wafer from the back grinding tape;
mounting the second side of the semiconductor wafer to a picking tape;
from the first side of the semiconductor wafer, etching through the predetermined distance between the second side of the semiconductor wafer and the depth of the plurality of trenches to singulate the plurality of die.
9. The method of claim 8 , wherein etching the plurality of trenches comprises plasma etching.
10. The method of claim 8 , wherein etching the plurality of trenches further comprises defining a pattern of the plurality of trenches using one of passivation material, metal material, photolithographic masking, temporary film, shadow masking, and any combination thereof.
11. The method of claim 8 , wherein the semiconductor wafer comprises silicon and etching the plurality of trenches and etching through the predetermined distance both further comprise using a Bosch deep reactive ion etch (DRIE) process.
12. The method of claim 8 , further comprising one of the following after etching the plurality of trenches:
forming a plurality of bumps on the plurality of die;
testing one or more of the plurality of die;
probing one or more of the plurality of die;
adding memory data to one or more of the plurality of die;
forming a solderable surface on a surface of one or more of the plurality of die; and
any combination thereof.
13. The method of claim 8 , wherein thinning the second side of the semiconductor wafer to the predetermined distance further comprises using a Taiko grinding process.
14. A method of singulating a plurality of die, the method comprising:
providing a semiconductor wafer comprising a plurality of die located on a first side of the semiconductor wafer, the plurality of die comprising a desired thickness;
etching a plurality of trenches into the semiconductor wafer from the first side of the semiconductor wafer, the plurality of trenches located adjacent a perimeter of the plurality of die and a depth of the plurality of trenches being greater than the desired thickness of the plurality of die;
mounting the first side of the semiconductor wafer to a back grinding tape;
thinning a second side of the semiconductor wafer to a predetermined distance between the second side of the semiconductor wafer and the depth of the plurality of trenches;
from the first side of the semiconductor wafer, etching through the predetermined distance between the second side of the semiconductor wafer and the depth of the plurality of trenches to singulate the plurality of die; and
transferring the plurality of die from the back grinding tape to a transporting tape.
15. The method of claim 14 , wherein etching the plurality of trenches comprises plasma etching.
16. The method of claim 14 , wherein etching the plurality of trenches further comprises defining a pattern of the plurality of trenches using one of passivation material, metal material, photolithographic masking, temporary film, shadow masking, and any combination thereof.
17. The method of claim 14 , wherein the semiconductor wafer comprises silicon and etching the plurality of trenches and etching through the predetermined distance both further comprise using a Bosch deep reactive ion etch (DRIE) process.
18. The method of claim 14 , further comprising one of the following after etching the plurality of trenches:
forming a plurality of bumps on the plurality of die;
testing one or more of the plurality of die;
probing one or more of the plurality of die;
adding memory data to one or more of the plurality of die;
forming a solderable surface on a surface of one or more of the plurality of die; and
any combination thereof.
19. The method of claim 14 , wherein thinning the second side of the semiconductor wafer to the predetermined distance further comprises using a Taiko grinding process.
20. The method of claim 14 , further comprising picking the plurality of die from the transporting tape.