Fast system state cloning
A system and method to create a clone of a source computing system, the system including the steps of selecting a memory space coupled to the source computing system, retrieving uncoded data from the selected memory space, encoding the uncoded data by use of a bit-marker-based encoding process executing on a backup server, storing encoded data in a protected memory coupled to the backup server, wherein the protected memory is protected from a power interruption, retrieving the encoded data from the protected memory; and decoding, the encoded data onto a target computing system, wherein the target computing system is separate from the source computing system.
1. A specialized computer architecture system comprising:
at least one random access memory;
a secondary energy source connected to the at least one random access memory, the secondary energy source configured to supply power to the at least one random access memory during a power interruption in order to maintain data stored in the at least one random access memory during the power interruption; and
a processor in electronic communication with the at least one random access memory through a communications bus to enable the processor to read and write data to the at least one random access memory;
the processor configured to access raw uncoded data;
the processor configured to generate encoded data based on encoding the raw uncoded data by using a bit-marker-based encoding process, wherein the bit-marker-based encoding process comprises decomposing the raw uncoded data into a plurality of data vectors and mapping each of the plurality of data vectors to a bit marker corresponding to a unique data vector;
the processor configured to store the encoded data in the at least one random access memory, wherein the encoded data comprises a plurality of bit markers corresponding to unique data vectors in the plurality of data vectors decomposed from the raw uncoded data;
the processor configured to process the raw uncoded data by accessing the encoded data stored in the at least one random access memory without the need for accessing a conventional persistent storage device;
the processor configured to access the encoded data stored in the at least one random access memory during a power interruption based on power supplied by the secondary energy source to the processor and the at least one random access memory, wherein the encoded data stored in the at least one random access memory is lost during a power interruption without power supplied to the at least one random access memory form the secondary energy source;
the processor configured to read the encoded data from the at least one random access memory;
the processor configured to extract the plurality of bit markers from the encoded data;
the processor configured to match each of the plurality of bit markers to a unique data vector stored in a bit-marker conversion table comprising bit-marker-data vector pairs; and
the processor configured to combine the matched unique data vectors to form a block of raw uncoded data.
2. The specialized computer architecture system of claim 1 , wherein the bit-marker-based encoding process further comprises storing a table of bit marker, unique data vector pairs.
3. The specialized computer architecture system of claim 2 , wherein the table is stored in the at least one random access memory and is persevered during a power interruption by power from the secondary energy source.
4. The specialized computer architecture system of claim 1 , wherein the secondary energy source comprises a large-capacitance capacitor.
5. The specialized computer architecture system of claim 1 , wherein the secondary energy source comprises a battery.
6. The specialized computer architecture system of claim 1 , wherein the at least one random access memory is configured to be a long-term electronic memory storage device.
7. The specialized computer architecture system of claim 1 , wherein the at least one random access memory is configured to be a high-capacity and fast transfer rate digital storage device.
8. The specialized computer architecture system of claim 1 , wherein the processor in electronic communication with the at least one random access memory transfer data through the communications bus at more than 57 gigabytes per second.
9. The specialized computer architecture system of claim 1 , wherein the bit-marker based encoding process uses fractal patterns for data encoding and decoding.
10. The specialized computer architecture system of claim 1 , wherein each of the plurality of bit markers can be reused to amplify an amount of raw uncoded data that can be stored in the at least one random access memory in an encoded form, wherein amplification is a ratio of a memory size of a bit marker to a memory size of raw data that corresponds to the bit marker multiplied by a number of instances of usage of the bit marker.
11. A specialized computer architecture system comprising:
at least one random access memory;
a secondary energy source connected to the at least one random access memory, the secondary energy source configured to supply power to the at least one random access memory during a power interruption in order to protect data stored on the at least one random access memory during the power interruption; and
a processor in electronic communication with the at least one random access memory through a communications bus to enable the processor to read and write data to the at least one random access memory, the processor configured to process raw data by:
encoding the raw uncoded data by using a bit-marker based encoding process, wherein the bit-marker-based encoding process comprises decomposing the raw uncoded data into a plurality of data vectors and mapping each of the plurality of data vectors to a bit marker corresponding to a unique data vector;
storing the encoded data in the at least one random access memory without the need for a conventional persistent storage device, wherein the encoded data comprises a plurality of bit markers corresponding to unique data vectors in the plurality of data vectors decomposed from the raw uncoded data;
preserving the encoded data stored in the at least one random access memory during a power interruption based on power supplied by the secondary energy source to the at least one random access memory, wherein the encoded data stored in the at least one random access memory is erased during a power interruption without power supplied to the at least one random access memory form the secondary energy source;
reading the encoded data from the at least one random access memory;
extracting the plurality of bit markers from the encoded data;
matching each of the plurality of bit markers to a unique data vector stored in a bit-marker conversion table comprising bit-marker-data vector pairs; and
combining the matched unique data vectors to form a block of raw uncoded data.
12. The specialized computer architecture system of claim 11 , wherein the bit-marker-based encoding process further comprises storing a table of bit marker, unique data vector pairs.
13. The specialized computer architecture system of claim 12 , wherein the table is stored in the at least one random access memory and is persevered during a power interruption by power from the secondary energy source.
14. The specialized computer architecture system of claim 11 , wherein the secondary energy source comprises a large-capacitance capacitor.
15. The specialized computer architecture system of claim 11 , wherein the secondary energy source comprises a battery.
16. The specialized computer architecture system of claim 11 , wherein the at least one random access memory is configured to be a long-term electronic memory storage device.
17. The specialized computer architecture system of claim 11 , wherein the at least one random access memory is configured to be a high-capacity and fast transfer rate digital storage device.
18. The specialized computer architecture system of claim 11 , wherein the processor in electronic communication with the at least one random access memory transfer data through the communications bus at more than 57 gigabytes per second.
19. The specialized computer architecture system of claim 11 , wherein the bit-marker based encoding process uses fractal patterns for data encoding and decoding.
20. The specialized computer architecture system of claim 11 , wherein each of the plurality of bit markers can be reused to amplify an amount of raw uncoded data that can be stored in the at least one random access memory in an encoded form, wherein amplification is a ratio of a memory size of a bit marker to a memory size of raw data that corresponds to the bit marker multiplied by a number of instances of usage of the bit marker.