Fin-based strap cell structure for improving memory performance

1. An integrated circuit device comprising:

a doped region of a first type dopant disposed in a substrate;

a FinFET disposed over the doped region of the first type dopant, wherein the FinFET includes:

a first semiconductor fin and first epitaxial source/drain features disposed in the first semiconductor fin,

an active gate structure that traverses the first semiconductor fin and is disposed between the first epitaxial source/drain features, and

wherein the first semiconductor fin extends from the substrate, the first semiconductor fin has a first width, the first epitaxial source/drain features are distinct from the first semiconductor fin, the first semiconductor fin is doped with the first type dopant, and the first epitaxial source/drain features are doped with a second type dopant that is different than the first type dopant;

a fin-based well strap disposed over the doped region of the first type dopant, wherein the fin-based well strap includes:

a second semiconductor fin and second epitaxial source/drain features disposed in the second semiconductor fin,

a dummy gate structure that traverses the second semiconductor fin and is disposed between the second epitaxial source/drain features, and

wherein the second semiconductor fin has a second width, the second epitaxial source/drain features are distinct from the second semiconductor fin, the second semiconductor fin is doped with the first type dopant, the second epitaxial source/drain features are doped with the first type dopant, and the second width is greater than the first width; and

a first device-level metal contact disposed on one of the first epitaxial source/drain features, a second device-level metal contact disposed on one of the second epitaxial source/drain features, and a third device-level metal contact disposed on the active gate structure, wherein the-one of the second epitaxial source/drain features is electrically connected to a voltage by the second device-level metal contact, such that the fin-based well strap connects the doped region to the voltage.

2. The integrated circuit device of claim 1 , wherein a ratio of the second width to the first width is greater than about 1.1.

3. The integrated circuit device of claim 2 , wherein the ratio of the second width to the first width is less than about 1.5.

4. The integrated circuit device of claim 1 , wherein a fin density of the FinFET is greater than a fin density of the fin-based well strap.

5. The integrated circuit device of claim 1 , wherein no device-level metal contact is disposed on the dummy gate structure.

6. The integrated circuit device of claim 1 , wherein:

the FinFET is located in a first area of the integrated circuit device; and

the fin-based well strap is located in a second area of the integrated circuit device, wherein the second area is spaced a distance from the first area and a third area is between the first area and the second area.

7. The integrated circuit device of claim 6 , wherein the doped region of the first type dopant is disposed in the substrate in the first area, the second area, and the third area, and further wherein the doped region extends along a fin-length direction from the first area to the third area to the second area.

8. The integrated circuit device of claim 1 , further comprising a multi-layer interconnect structure that includes:

the first device-level metal contact, the second device-level metal contact, and the third device-level metal contact;

a first metal via disposed on the first device-level metal contact;

a second metal via disposed on the second device-level metal contact; and

a first metal line, wherein the first metal via electrically connects the one of the first epitaxial source/drain features to the first metal line and the second metal via electrically connects the one of the second epitaxial source/drain features to the first metal line.

9. The integrated circuit device of claim 1 , wherein the FinFET is a first FinFET, the fin-based well strap is a first fin-based well strap, the doped region is a first doped region, the voltage is a first voltage, the active gate structure is a first active gate structure, and the dummy gate structure is a first dummy gate structure, the integrated circuit device further comprising:

a second doped region of the second type dopant disposed in the substrate;

a second FinFET disposed over the second doped region of the second type dopant, wherein the second FinFET includes:

a third semiconductor fin and third epitaxial source/drain features disposed in the third semiconductor fin, wherein the third semiconductor fin extends from the substrate and the third epitaxial source/drain features are distinct from the third semiconductor fin,

a second active gate structure that traverses the third semiconductor fin and is disposed between the third epitaxial source/drain features, and

the third semiconductor fin has a third width, the third semiconductor fin is doped with the second type dopant, and the third epitaxial source/drain features are doped with the first type dopant;

a second fin-based well strap disposed over the second doped region, wherein the second fin-based well strap includes:

a fourth semiconductor fin and fourth epitaxial source/drain features disposed in the fourth semiconductor fin, wherein the fourth semiconductor fin extends from the substrate and the fourth epitaxial source/drain features are distinct from the fourth semiconductor fin,

a second dummy gate structure that traverses the fourth semiconductor fin and is disposed between the fourth epitaxial source/drain features, and

the fourth semiconductor fin has a fourth width, the fourth semiconductor fin is doped with the second type dopant, the fourth epitaxial source/drain features are doped with the second type dopant, and the fourth width is greater than the third width; and

a fourth device-level metal contact disposed on one of the third epitaxial source/drain features, a fifth device-level metal contact disposed on one of the fourth epitaxial source/drain features, and a sixth device-level metal contact disposed on the second active gate structure, wherein the one of the fourth epitaxial source/drain features is electrically connected to a second voltage by the fifth device-level metal contact, such that the second fin-based well strap connects the second doped region to the second voltage.

10. A memory array comprising:

a first row of well strap cells and a second row of well strap cells;

a plurality of memory cells arranged in columns and rows, wherein the plurality of memory cells are disposed between the first row of well strap cells and the second row of well strap cells, such that each column of memory cells is disposed between a first well strap cell and a second well strap cell;

wherein each of the memory cells include a FinFET disposed over a doped region of a first type dopant in a substrate, wherein the FinFET includes:

a first semiconductor fin having a first width doped with the first type dopant and first epitaxial source/drain features of a second type dopant,

an active gate structure that traverses the first semiconductor fin and is disposed between the first epitaxial source/drain features, and

wherein the first semiconductor fin extends from the substrate and the first epitaxial source/drain features are distinct from the first semiconductor fin; and

wherein the first well strap cell and the second well strap cell each include a fin-based well strap disposed over the doped region of the first type dopant in the substrate, wherein the fin-based well strap includes:

a second semiconductor fin having a second width doped with the first type dopant and second epitaxial source/drain features of the first type dopant,

a dummy gate structure that traverses the second semiconductor fin and is disposed between the second epitaxial source/drain features,

wherein the second semiconductor fin extends from the substrate, the second width is greater than the first width, and the second epitaxial source/drain features are distinct from the second semiconductor fin, and

wherein a metal contact is disposed on one of the second epitaxial source/drain features and the metal contact is electrically connected to a voltage, such that the fin-based well strap connects the doped region of the first type dopant to the voltage.

11. The memory array of claim 10 , wherein a ratio of the second width to the first width is greater than about 1.1.

12. The memory array of claim 10 , wherein the first semiconductor fin has a first dopant concentration of the first type dopant and the second semiconductor fin has a second dopant concentration of the first type dopant, wherein the second dopant concentration is at least three times greater than the first dopant concentration.

13. The memory array of claim 10 , wherein:

the first semiconductor fin, the first epitaxial source/drain features, and the active gate structure are disposed entirely within the memory cells; and

the second semiconductor fin, the second epitaxial source/drain features, and the dummy gate structure are disposed entirely within the well strap cells.

14. The memory array of claim 10 , wherein the FinFET is a first FinFET, the doped region is a first doped region, the fin-based well strap is a first fin-based well strap, the active gate structure is a first active gate structure, the dummy gate structure is a first dummy gate structure, and the metal contact is a first metal contact, and further wherein:

each of the memory cells include a second FinFET disposed over a second doped region of the second type dopant in the substrate, wherein the second FinFET includes:

a third semiconductor fin having a third width doped with the second type dopant and third epitaxial source/drain features of the first type dopant, wherein the third semiconductor fin extends from the substrate and the third epitaxial source/drain features are distinct from the third semiconductor fin, and

a second active gate structure that traverses the third semiconductor fin and is disposed between the third epitaxial source/drain features; and

the first well strap cell and the second well strap cell each include a second fin-based well strap disposed over the second doped region, wherein the second fin-based well strap includes:

a fourth semiconductor fin having a fourth width doped with the second type dopant and fourth epitaxial source/drain features of the second type dopant,

a second dummy gate structure that traverses the fourth semiconductor fin and is disposed between the fourth epitaxial source/drain features,

wherein the fourth semiconductor fin extends from the substrate, the fourth width is greater than the third width, and the fourth epitaxial source/drain features are distinct from the fourth semiconductor fin, and

wherein a second metal contact is disposed on one of the fourth epitaxial source/drain features and the second metal contact is electrically connected to a second voltage, such that the second fin-based well strap connects the second doped region to the second voltage.

15. The memory array of claim 14 , wherein a ratio of the second width to the first width is about 1.1 to about 1.5 and a ratio of the fourth width to the third width is about 1.1 to about 1.5.

16. The memory array of claim 14 , wherein the second FinFET is disposed adjacent to the first FinFET along a fin width direction, and the first fin-based well strap is not disposed adjacent to the second fin-based well strap along the fin width direction.

17. The memory array of claim 14 , wherein:

the first semiconductor fin has a first dopant concentration of the first type dopant, the second semiconductor fin has a second dopant concentration of the first type dopant, the third semiconductor fin has a third dopant concentration of the second type dopant, and the fourth semiconductor fin has a fourth dopant concentration of the second type dopant; and

the second dopant concentration is at least three times greater than the first dopant concentration and the fourth dopant concentration is at least three times greater than the third dopant concentration.

18. The memory array of claim 14 , wherein the first FinFET is a pull-down transistor, and the second FinFET is a pull-up transistor.

19. The memory array of claim 10 , wherein the plurality of memory cells include a first memory cell array and a second memory cell array, the memory array further comprising a third row of well strap cells disposed between the first memory cell array and the second memory cell array.

20. A device including:

a memory cell that includes a plurality of fin-like field effect transistors (FinFETs), wherein the plurality of FinFETs include at least:

a p-type FinFET disposed over an n-well disposed in a semiconductor substrate, wherein the p-type FinFET includes a first semiconductor fin doped with an n-type dopant, first epitaxial source/drain features doped with a p-type dopant, and a first gate disposed over the first semiconductor fin and between the first epitaxial source/drain features, wherein the first semiconductor fin has a first width, the first gate is electrically connected to a first voltage by a first metal interconnect and the first semiconductor fin is distinct from the first epitaxial source/drain features, and

an n-type FinFET disposed over a p-well disposed in the semiconductor substrate, wherein the n-type FinFET includes a second semiconductor fin doped with the p-type dopant, second epitaxial source/drain features doped with the n-type dopant, and a second gate disposed over the second semiconductor fin and between the second epitaxial source/drain features, wherein the second semiconductor fin has a second width, the first gate is electrically connected to a second voltage by a second metal interconnect and the second semiconductor fin is distinct from the second epitaxial source/drain features; and

a fin-based well strap cell that includes:

a fin-based n-type well strap disposed over the n-well, wherein the fin-based n-type well strap includes a third semiconductor fin doped with the n-type dopant, third epitaxial source/drain features doped with the n-type dopant, and a third gate disposed over the third semiconductor fin and between the third epitaxial source/drain features, wherein the third semiconductor fin has a third width, the third gate is not electrically connected to a voltage by a metal interconnect, the third semiconductor fin is distinct from the third epitaxial source/drain features, the third width is greater than the first width, and one of the third epitaxial source/drain features is electrically connected to a third voltage by a third metal interconnect, such that the fin-based n-type well strap connects the n-well to the third voltage, and

a fin-based p-type well strap disposed over the p-well, wherein the fin-based p-type well strap includes a fourth semiconductor fin doped with the p-type dopant, fourth epitaxial source/drain features doped with the p-type dopant, and a fourth gate disposed over the fourth semiconductor fin and between the fourth epitaxial source/drain features, wherein the fourth semiconductor fin has a fourth width, the fourth gate is not electrically connected to a voltage by a metal interconnect, the fourth semiconductor fin is distinct from the fourth epitaxial source/drain features, the fourth width is greater than the second width, and one of the fourth epitaxial source/drain features is electrically connected to a fourth voltage by a fourth metal interconnect, such that the fin-based p-type well strap connects the p-well to the fourth voltage.