IP Library Granted Patent US 10,741,487
Granted Patent B2
US 10,741,487 · App. 15/961,642 · Granted Aug 11, 2020

SOI substrate and related methods

Inventors: Michael J. Seddon (Gilbert, AZ); Mark Griswold (Gilbert, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/5222H01L21/0226H01L21/786H01L23/12H01L23/34
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Quick Facts
Patent No.
US 10,741,487
App. No.
15/961,642
Granted
Aug 11, 2020
Kind
B2
Abstract

Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.

Claims (23)

1. A method of making a silicon-on-insulator (SOI) die, the method comprising:

forming a ring around a perimeter of a second side of a silicon substrate through backgrinding the second side of the silicon substrate to a desired substrate thickness;

depositing an insulative layer onto the second side of the silicon substrate after backgrinding;

completely removing the ring around the perimeter of the second side of the silicon substrate; and

singulating the silicon substrate into a plurality of SOI die.

2. The method of claim 1 , further comprising forming a plurality of semiconductor devices on the first side of the silicon substrate, the first side opposite the second side of the silicon substrate.

3. The method of claim 1 , wherein the plurality of SOI die are less than 35 micrometers thick.

4. The method of claim 1 , further comprising stress relief etching the second side of the silicon substrate.

5. The method of claim 1 , wherein the insulative layer is deposited using one of co-evaporation and co-sputtering.

6. The method of claim 5 , further comprising dissipating heat through a heat dissipation device during deposition of the insulative layer.

7. The method of claim 5 , wherein the one of co-evaporation and co-sputtering occur at temperatures that do not require heat dissipation.

8. The method of claim 1 , wherein the method does not comprise implanting hydrogen.

9. The method of claim 1 , wherein no sacrificial carrier substrate is used to make the SOT die.

10. A method of making a silicon-on-insulator (SOI) die, the method comprising:

forming a ring around a perimeter of a second side of a silicon substrate through backgrinding the second side of the silicon substrate to a desired substrate thickness;

depositing a conductive layer onto the second side of the silicon substrate;

depositing an insulative layer over the conductive layer;

removing the ring around the perimeter of the second side of the silicon substrate; and

singulating the silicon substrate into a plurality of SOI die.

11. The method of claim 10 , further comprising patterning the conductive layer.

12. The method of claim 10 , wherein the conductive layer comprises titanium.

13. The method of claim 10 , wherein the silicon substrate is thinned to less than 35 micrometers.

14. The method of claim 10 , wherein the insulative layer is deposited using one of co-evaporation and co-sputtering.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 047864, FRAME 0611 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064077/0298 →
PATENT SECURITY AGREEMENT Recorded Oct 16, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047864/0611 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2018
From: SEDDON, MICHAEL J.; GRISWOLD, MARK
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 045626/0649 →
Continuity (1)
Related Publication 20190326211A1 · Oct 24, 2019