Bootstrap capacitor charging circuit for GaN devices
GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.
1. A charging circuit comprising:
a GaN-based semiconductor circuit configured to allow current flow from a ground referenced power supply node to a first floating power supply terminal, wherein the semiconductor circuit comprises:
a first enhancement-mode transistor, comprising:
a gate configured to be controlled by a gate drive circuit control signal,
a source directly connected to the ground referenced power supply node, and
a drain directly connected to the first floating power supply terminal; and
a second enhancement-mode transistor, comprising:
a gate connected to the ground referenced power supply node,
a source directly connected to the ground referenced power supply node, and
a drain directly connected to the first floating power supply terminal.
2. The charging circuit of claim 1 , wherein the semiconductor circuit is configured to be capable of operating with the first floating power supply terminal at a voltage that is at least 20 volts greater than a voltage of the ground referenced power supply node.
3. The charging circuit of claim 1 , wherein the semiconductor circuit is used in conjunction with a half bridge circuit comprising:
a low side GaN-based transistor having a low side transistor control gate configured to receive a low side gate signal from a ground referenced gate drive circuit; and
a high side GaN-based transistor having a high side transistor control gate configured to receive a high side gate signal from a gate drive circuit that is referenced to a second floating power supply terminal.
4. The charging circuit of claim 3 , wherein the second floating power supply terminal is a switch node of the half bridge circuit.
5. The charging circuit of claim 3 , wherein a capacitor is connected between the first floating power supply terminal and the second floating power supply terminal.
6. The charging circuit of claim 3 , wherein the gate drive circuit control signal is in phase with the low side gate signal.
7. The charging circuit of claim 3 , further comprising a delay circuit configured to turn on the first enhancement-mode transistor after the low side GaN-based transistor turns on.
8. The charging circuit of claim 3 , further comprising a delay circuit configured to turn off the first enhancement-mode transistor before the low side GaN-based transistor turns off.
9. An electronic power conversion component comprising:
a package base; and
one or more GaN-based dies secured to the package base, each including a charging circuit comprising:
a GaN-based semiconductor circuit configured to allow current flow from a ground referenced power supply node to a first floating power supply terminal, wherein the semiconductor circuit comprises:
a first enhancement-mode transistor, comprising:
a gate configured to be controlled by a gate drive circuit control signal,
a source directly connected to the ground referenced power supply node, and
a drain directly connected to the first floating power supply terminal; and
a second enhancement-mode transistor, comprising:
a gate connected to the ground referenced power supply node,
a source directly connected to the ground referenced power supply node, and
a drain directly connected to the first floating power supply terminal.
10. The component of claim 9 , wherein the semiconductor circuit is configured to be capable of operating with the first floating power supply terminal at a voltage that is at least 20 volts greater than a voltage of the ground referenced power supply node.
11. The component of claim 9 , wherein the semiconductor circuit is used in conjunction with a half bridge circuit comprising:
a low side GaN-based transistor having a low side transistor control gate configured to receive a low side gate signal from a ground referenced gate drive circuit; and
a high side GaN-based transistor having a high side transistor control gate configured to receive a high side gate signal from a gate drive circuit that is referenced to a second floating power supply terminal.
12. The component of claim 11 , wherein the second floating power supply terminal is a switch node of the half bridge circuit.
13. The component of claim 11 , wherein a capacitor is connected between the first floating power supply terminal and the second floating power supply terminal.
14. The component of claim 11 , wherein the gate drive circuit control signal is in phase with the low side gate signal.
15. The component of claim 11 , wherein each semiconductor circuit comprises a delay circuit configured to turn on the first enhancement-mode transistor after the low side GaN-based transistor turns on.
16. The component of claim 11 , wherein each semiconductor circuit comprises a delay circuit configured to turn off the first enhancement-mode transistor before the low side GaN-based transistor turns off.
17. A method of using a charging circuit, the method comprising:
allowing current to flow from a ground referenced power supply node to a first floating power supply terminal with a semiconductor circuit, wherein the semiconductor circuit comprises:
a first enhancement-mode transistor, comprising:
a gate configured to be controlled by a gate drive circuit control signal,
a source directly connected to the ground referenced power supply node, and
a drain directly connected to the first floating power supply terminal,
wherein the first enhancement-mode transistor is configured to allow current to flow from the ground referenced power supply to the first floating power supply terminal in response to the gate drive circuit control signal; and
a second enhancement-mode transistor, comprising:
a gate connected to the ground referenced power supply node,
a source directly connected to the ground referenced power supply node, and
a drain directly connected to the first floating power supply terminal.
18. The method of claim 17 , further comprising providing a potential to the first floating power supply terminal which is at least 20 volts greater than a voltage of the ground referenced power supply node.
19. The method of claim 17 , wherein the first enhancement-mode transistor is configured to prevent current from flowing from the ground referenced power supply node to the first floating power supply terminal in response to the gate drive circuit control signal.
20. The method of claim 17 , wherein the semiconductor circuit is used in conjunction with a half bridge circuit comprising the ground referenced power supply node and the first floating power supply terminal.