Structure for reducing compound semiconductor wafer distortion
An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer and at least one stress balance layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein a thermal conductivity of the at least one stress balance layer is greater than or equal to 10 W/m-K. The stress suffered by the compound semiconductor wafer is balanced by the at least one stress balance layer, so that the distortion of the compound semiconductor wafer is reduced.
1. An improved structure for reducing compound semiconductor wafer distortion, comprising:
a contact metal layer formed on a bottom surface of a compound semiconductor wafer;
at least one stress balance layer formed on a bottom surface of said contact metal layer, wherein a thermal conductivity of said at least one stress balance layer is greater than or equal to 10 W/m-K; and
a die attachment layer formed on a bottom surface of said at least one stress balance layer;
wherein the stress suffered by said compound semiconductor wafer is balanced by said at least one stress balance layer, so that the distortion of said compound semiconductor wafer is reduced.
2. The improved structure for reducing compound semiconductor wafer distortion according to claim 1 , wherein said contact metal layer is made by at least one material selected from the group consisting of: Pd, Ge, Ni, Ti, Pt, Au, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mn, Fe, Co, Ru, Rh, Cu, Al, Zn, In, Sn, Sb, Mg, Pb, Ag, TiW alloy and TiWN alloy.
3. The improved structure for reducing compound semiconductor wafer distortion according to claim 1 , wherein said contact metal layer has a thickness greater than or equal to 10 nm and less than or equal to 1000 nm.
4. The improved structure for reducing compound semiconductor wafer distortion according to claim 1 , wherein said at least one stress balance layer is made of at last one electrically nonconductive material.
5. The improved structure for reducing compound semiconductor wafer distortion according to claim 4 , wherein said at least one stress balance layer is made by at least one material selected from the group consisting of: AlN, SiC, ITO, diamond and InP.
6. The improved structure for reducing compound semiconductor wafer distortion according to claim 1 , wherein said at least one stress balance layer has a thickness greater than or equal to 50 nm and less than or equal to 5000 nm.
7. The improved structure for reducing compound semiconductor wafer distortion according to claim 1 , wherein said at least one stress balance layer is formed on said bottom surface of said contact metal layer by sputtering, PVD, PECVD, CVD or ALD.
8. The improved structure for reducing compound semiconductor wafer distortion according to claim 1 , wherein said die attachment layer is made by at least one material selected from the group consisting of: Au or Au alloy, Ag or Ag alloy, Sn or Sn alloy, and silver conductive epoxy adhesive.
9. The improved structure for reducing compound semiconductor wafer distortion according to claim 1 , further comprising an epitaxial structure, wherein said epitaxial structure is formed on a top surface of said compound semiconductor wafer.
10. An improved structure for reducing compound semiconductor wafer distortion, comprising:
a contact metal layer formed on a bottom surface of a compound semiconductor wafer; and
at least one stress balance layer formed on a bottom surface of said contact metal layer, wherein a thermal conductivity of said at least one stress balance layer is greater than or equal to 10 W/m-K, wherein said at least one stress balance layer is made of at least one electrically nonconductive material;
wherein the stress suffered by said compound semiconductor wafer is balanced by said at least one stress balance layer, so that the distortion of said compound semiconductor wafer is reduced.
11. The improved structure for reducing compound semiconductor wafer distortion according to claim 10 , wherein said at least one stress balance layer is made by at least one material selected from the group consisting of: AlN, SiC, ITO, diamond and InP.
12. The improved structure for reducing compound semiconductor wafer distortion according to claim 10 , wherein said at least one stress balance layer is formed on said bottom surface of said contact metal layer by sputtering, PVD, PECVD, CVD or ALD.
13. The improved structure for reducing compound semiconductor wafer distortion according to claim 10 , wherein said at least one stress balance layer has a thickness greater than or equal to 50 nm and less than or equal to 5000 nm.
14. The improved structure for reducing compound semiconductor wafer distortion according to claim 10 , wherein said contact metal layer is made by at least one material selected from the group consisting of: Pd, Ge, Ni, Ti, Pt, Au, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mn, Fe, Co, Ru, Rh, Cu, Al, Zn, In, Sn, Sb, Mg, Pb, Ag, TiW alloy and TiWN alloy.
15. The improved structure for reducing compound semiconductor wafer distortion according to claim 10 , wherein said contact metal layer has a thickness greater than or equal to 10 nm and less than or equal to 1000 nm.
16. The improved structure for reducing compound semiconductor wafer distortion according to claim 10 , further comprising an epitaxial structure, wherein said epitaxial structure is formed on a top surface of said compound semiconductor wafer.
17. An improved structure for reducing compound semiconductor wafer distortion, comprising:
a contact metal layer formed on a bottom surface of a compound semiconductor wafer; and
at least one stress balance layer formed on a bottom surface of said contact metal layer, wherein a thermal conductivity of said at least one stress balance layer is greater than or equal to 10 W/m-K, wherein each of said at least one stress balance layer is made by at least one material selected from the group consisting of: Au or Au alloy, WN alloy, AlCu alloy, Fe alloy, Sn or Sn alloy, Mg or Mg alloy, brass, graphite, stainless steel, monel, Pt, Zn and Nb;
wherein the stress suffered by said compound semiconductor wafer is balanced by said at least one stress balance layer, so that the distortion of said compound semiconductor wafer is reduced.
18. The improved structure for reducing compound semiconductor wafer distortion according to claim 17 , wherein said at least one stress balance layer is formed on said bottom surface of said contact metal layer by sputtering, electroplating, PVD, PECVD, CVD or ALD.
19. The improved structure for reducing compound semiconductor wafer distortion according to claim 17 , wherein said at least one stress balance layer has a thickness greater than or equal to 50 nm and less than or equal to 5000 nm.
20. The improved structure for reducing compound semiconductor wafer distortion according to claim 17 , wherein said contact metal layer is made by at least one material selected from the group consisting of: Zr, Hf, V, Nb, W, Mn, Fe, Co, Ru, Rh, Cu, Zn, In, Sn, Sb, Mg, Pb, TiW alloy and TiWN alloy.
21. The improved structure for reducing compound semiconductor wafer distortion according to claim 17 , wherein said contact metal layer has a thickness greater than or equal to 10 nm and less than or equal to 1000 nm.
22. The improved structure for reducing compound semiconductor wafer distortion according to claim 17 , further comprising an epitaxial structure, wherein said epitaxial structure is formed on a top surface of said compound semiconductor wafer.
23. The improved structure for reducing compound semiconductor wafer distortion according to claim 17 , wherein said compound semiconductor wafer is made by one material selected from the group consisting of: GaAs, sapphire, InP, GaP, SiC, GaN, IAN, ZnSe, InAs, and GaSb.
24. The improved structure for reducing compound semiconductor wafer distortion according to claim 17 , wherein said compound semiconductor wafer has a thickness greater than or equal to 25 μm and less than or equal to 350 μm.
25. The improved structure for reducing compound semiconductor wafer distortion according to claim 17 , wherein said compound semiconductor wafer has a diameter greater than or equal to 3 inches.
26. The improved structure for reducing compound semiconductor wafer distortion according to claim 1 , wherein said compound semiconductor wafer is made by one material selected from the group consisting of: GaAs, sapphire, InP, GaP, SiC, GaN, AlN, ZnSe, InAs, and GaSb.
27. The improved structure for reducing compound semiconductor wafer distortion according to claim 1 , wherein said compound semiconductor wafer has a thickness greater than or equal to 25 μm and less than or equal to 350 μm.
28. The improved structure for reducing compound semiconductor wafer distortion according to claim 1 , wherein said compound semiconductor wafer has a diameter greater than or equal to 3 inches.
29. The improved structure for reducing compound semiconductor wafer distortion according to claim 10 , wherein said compound semiconductor wafer is made by one material selected from the group consisting of: GaAs, sapphire, InP, GaP, SiC, GaN, AlN, ZnSe, InAs, and GaSb.
30. The improved structure for reducing compound semiconductor wafer distortion according to claim 10 , wherein said compound semiconductor wafer has a thickness greater than or equal to 25 μm and less than or equal to 350 μm.
31. The improved structure for reducing compound semiconductor wafer distortion according to claim 10 , wherein said compound semiconductor wafer has a diameter greater than or equal to 3 inches.
32. The improved structure for reducing compound semiconductor wafer distortion according to claim 17 , wherein said contact metal layer is made by at least one material selected from the group consisting of: Pd, Ge, Ni, Ti, Pt, Au, Ta, Cr, Mo, Al, and Ag.
33. An improved structure for reducing compound semiconductor wafer distortion, comprising:
a contact metal layer formed on a bottom surface of a compound semiconductor wafer, wherein said contact metal layer is made by at least one material selected from the group consisting of: Zr, Hf, V, Nb, W, Mn, Fe, Co, Ru, Rh, Cu, Zn, In, Sn, Sb, Mg, Pb, TiW alloy and TiWN alloy; and
at least one stress balance layer formed on a bottom surface of said contact metal layer, wherein a thermal conductivity of said at least one stress balance layer is greater than or equal to 10 W/m-K, wherein each of said at least one stress balance layer is made of TiWN alloy.