Epitaxial structures for fin-like field effect transistors
Epitaxial structures of a fin-like field effect transistor (FinFET) device includes a substrate, a fin structure including two fins, inner and outer fin spacers formed along both sidewalls of the fins, and isolation regions formed around the fins. The FinFET device further includes a gate structure formed over the fin structure and an epitaxial structure formed over the fin structure in a source/drain region. The epitaxial structure is formed by merging the fins with at least one epitaxial semiconductor layer and includes an air gap having a volume determined by the height and separation distance of the inner fin spacers.
1. A semiconductor structure, comprising:
a fin structure having a first fin and a second fin formed on a semiconductor substrate, wherein the first fin and the second fin have a height H f in a channel region thereof;
inner fin spacers formed along inner sidewalls of the first and the second fins, wherein the inner fin spacers have a height H i ;
outer fin spacers formed along outer sidewalls of the first and the second fins, wherein the outer fin spacers have a height H o , H o being substantially less than H i ; and
an epitaxial structure formed over both the first and the second fins, wherein the epitaxial structure encloses an air gap formed by the inner fin spacers, the air gap having at least a width P, wherein P is a separation distance between opposing sidewalls of the inner fin spacers, wherein the air gap includes:
a first portion between the inner fin spacers of the first and the second fins, wherein the first portion has height H i ; and
a second portion above the first portion, wherein the second portion has a height H a , wherein a sum of H i and H a is about 30% to about 80% of the height H f .
2. The semiconductor structure of claim 1 , wherein the epitaxial structure includes a plurality of facets, wherein the facet directly above top surfaces of the first and the second fins is substantially parallel to the top surfaces of the first and the second fins.
3. The semiconductor structure of claim 1 , wherein the epitaxial structure includes at least one doped epitaxial semiconductor layer.
4. The semiconductor structure of claim 3 , wherein the epitaxial structure includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, wherein the first, the second, and the third epitaxial layers include different dopant concentrations.
5. The semiconductor structure of claim 4 , wherein the first epitaxial layer grows on top surfaces of the first and the second fins such that a top surface of the first epitaxial layer is coplanar with top surfaces of the outer fin spacers.
6. The semiconductor structure of claim 1 , wherein the height H a of the second portion of the air gap above the inner fin spacers is about ⅓ to about ½ of H i .
7. The semiconductor structure of claim 1 , wherein the inner fin spacers do not physically contact either of the first and the second fins in a source/drain region.
8. A semiconductor structure, comprising:
a semiconductor substrate;
a fin structure comprising a first fin and a second fin formed on the semiconductor substrate, wherein each of the first and the second fins have a height H f in a channel region thereof, wherein an inner fin spacer and an outer fin spacer are formed vertically along two opposing sidewalls of each of the first and the second fins, and wherein the inner fin spacer of the first fin is disposed adjacent to the inner fin spacer of the second fin, the inner fin spacers of the first and the second fins having a height H i and separated by a distance P, both of the outer fin spacers having a height H o , wherein H i is substantially greater than H o ;
a gate structure formed over the fin structure; and
an epitaxial structure formed in a source region and a drain region of the fin structure, wherein the epitaxial structure merges the first and the second fins with at least one epitaxial semiconductor layer, and wherein the at least one epitaxial semiconductor layer and the inner fin spacers form an air gap, wherein the air gap includes:
a first portion between the inner fin spacers of the first and the second fins, wherein the first portion has height H i ; and
a second portion above the first portion, wherein the second portion has a height H a , wherein a sum of H i and H a is about 30% to about 80% of the height H f .
9. The semiconductor structure of claim 8 , wherein the air gap has a height of at least H i and a width of at least P.
10. The semiconductor structure of claim 8 , further comprising isolation regions formed over the semiconductor substrate to isolate the first and the second fins, wherein a top surface of the first and the second fins is above a top surface of the isolation regions.
11. The semiconductor structure of claim 8 , further comprising isolation regions formed over the semiconductor substrate to isolate the first and the second fins, wherein a top surface of the first and the second fins is below a top surface of the isolation regions.
12. The semiconductor structure of claim 8 , wherein a top surface of the epitaxial structure is substantially parallel to a top surface of the fin structure.
13. A device comprising:
a first fin structure and a second fin structure disposed over a substrate, wherein each of the first fin structure and the second fin structure have a height H f in a channel region thereof, the first fin structure having an inner sidewall surface, an outer sidewall surface opposing the inner sidewall surface and a top surface extending from the inner sidewall surface to the outer sidewall surface;
an inner dielectric spacer disposed along the inner sidewall surface of the first fin structure, the inner dielectric spacer extending to a first height H i above the substrate;
an outer dielectric spacer disposed along the outer sidewall surface of the first fin structure, the outer dielectric spacer extending to a second height H o above the substrate, the second height H o being less than the first height H i ; and
an epitaxial semiconductor structure disposed over the first fin structure and the second fin structure, wherein the epitaxial semiconductor structure encloses an air gap disposed between the first fin structure and the second fin structure, wherein the air gap includes:
a first portion adjacent to the inner dielectric spacer extending to the first height H i ; and
a second portion above the first portion, wherein the second portion has a height H a , wherein a sum of H i and H a is about 30% to about 80% of the height H f .
14. The device of claim 13 , wherein the epitaxial semiconductor structure includes a first epitaxial material, a second epitaxial material and a third epitaxial material,
wherein the first epitaxial material, the second epitaxial material and the third epitaxial material are different from each other.
15. The device of claim 14 , wherein the first epitaxial material, the second epitaxial material and the third epitaxial material include the same dopant,
wherein a dopant concentration in the first epitaxial material is different than a dopant concentration in the second epitaxial material, and
wherein the dopant concentration in the second epitaxial material is different than a dopant concentration in the third epitaxial material.
16. The device of claim 13 , wherein the inner dielectric spacer is a first inner dielectric spacer, wherein the inner sidewall surface is a first inner sidewall surface, wherein the outer dielectric spacer is a first outer dielectric spacer, and wherein the outer sidewall surface is a first outer sidewall surface, further comprising:
a second inner dielectric spacer disposed along a second inner sidewall surface of the second fin structure, the second inner dielectric spacer extending to the first height H i above the substrate; and
a second outer dielectric spacer disposed along a second outer sidewall surface of the second fin structure, the second outer dielectric spacer extending to the second height H o above the substrate, and
wherein the second outer sidewall surface of the second fin structure opposes the second inner sidewall surface of the second fin structure.
17. The device of claim 16 , wherein the air gap extends from the first inner dielectric spacer to the second inner dielectric spacer.
18. The device of claim 16 , wherein the first inner dielectric spacer has opposing sidewall surfaces, and
wherein the epitaxial semiconductor structure physically contacts one of the opposing sidewall surfaces while the air gap interfaces with the other one of the opposing sidewall surfaces of the first inner dielectric spacer.
19. The device of claim 16 , wherein the air gap extends over a top surface of the first inner dielectric spacer, the top surface of the first inner dielectric spacer facing away from the substrate.
20. The device of claim 13 , wherein the air gap interfaces with the inner dielectric spacer.