IP Library › Granted Patent US 10,396,793
Granted Patent B2
US 10,396,793 · App. 15/962,895 · Granted Aug 27, 2019

Level shift circuit

Inventor: Shuji Furuichi (Tokyo, JP)
Assignee: LAPIS Semiconductor Co., Ltd.
H03K19/0185H03K3/011H03K3/012H03K3/35613H03K3/356104H03K3/356182
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Quick Facts
Patent No.
US 10,396,793
App. No.
15/962,895
Granted
Aug 27, 2019
Kind
B2
Abstract

A level shift circuit includes: a constant-current generation unit; a current mirror unit that flows the constant-current through first and second lines; and a level shift unit that receives first and second input signals, the first input signal being varied between first and second logic levels and having first and second potentials at the first and second logic levels respectively, the second input signal being a phase-inverted signal of the first input signal, the level shift unit producing first and second output signals that are acquired by shifting a signal level at the first logic level of the first and second input signals from the first potential to the power supply potential, the level shift unit outputting the first output signal from a node on the second line and outputting the second output signal from a node on the first line. The constant-current generation unit includes a current adjustment circuit which varies the constant current value depending on a variation in the first potential.

Claims (27)

1. A level shift circuit comprising:

a constant-current generation unit configured to generate a constant current on a basis of a high power supply voltage and a low power supply voltage;

a current mirror unit configured to flow said constant current through a first line and a second line; and

a level shift unit configured to receive a first input signal and a second input signal being inputted, the first input signal being changed in signal level to a high logic having a potential level of said low power supply voltage and a low logic level having a potential level of a ground potential,

the second input signal being a phase-inverted signal of said first input signal,

the level shift unit being configured to produce a first output signal and a second output signal that are acquired by shifting the signal level at said high logic level of said first input signal and said second input signal from said potential level of said low power supply voltage to a potential level of said high power supply voltage,

the level shift unit being further configured to output said first output signal from a second node on said second line and output said second output signal from a first node on said first line, wherein

said constant-current generation unit includes:

a current adjustment transistor to which said low power supply voltage is applied, the current adjustment transistor being configured to vary a value of said constant current depending on a variation in said low power supply voltage;

first to nth transistors (n is 2 or 3) of a first conductivity type that are connected in series to said high power supply voltage; and

at least one resistor element connected between said nth transistor and said current adjustment transistor;

said first to nth transistors constitute an n-stage current mirror circuit with each gate terminal connected to said current mirror unit; and

said current adjustment transistor is a transistor of a second conductivity type opposite in conductivity type to said first conductivity type, and has a source terminal connected to the ground potential and a gate terminal to which said low power supply voltage is applied.

2. A level shift circuit comprising:

a constant-current generation unit configured to generate a constant current on a basis of a high power supply voltage and a low power supply voltage;

a current mirror unit configured to flow said constant current through a first line and a second line; and

a level shift unit configured to receive a first input signal and a second input signal being inputted, the first input signal being changed in signal level to a high logic having a potential level of said low power supply voltage and a low logic level having a potential level of a ground potential,

the second input signal being a phase-inverted signal of said first input signal,

the level shift unit being configured to produce a first output signal and a second output signal that are acquired by shifting the signal level at said high logic level of said first input signal and said second input signal from said potential level of said low power supply voltage to a potential level of said high power supply voltage,

the level shift unit being further configured to output said first output signal from a second node on said second line and output said second output signal from a first node on said first line, wherein

said constant-current generation unit includes:

a current adjustment transistor to which said low power supply voltage is applied, the current adjustment transistor being configured to vary a value of said constant current depending on a variation in said low power supply voltage;

first to nth transistors (n is 2 or 3) of a first conductivity type that are connected in series to said high power supply voltage;

(n+1)th to (2n)th transistors of said first conductivity type of which gate terminals are connected to respective gate terminals of said first to nth transistors to constitute transistor pairs and which are connected in series to said high power supply voltage; and

at least one resistor element connected between said (2n)th transistor and the ground potential;

said first to nth transistors constitute an n-stage current mirror circuit with each gate terminal connected to said current mirror unit; and

said current adjustment transistor is a transistor of a second conductivity type opposite in conductivity type to said first conductivity type, and has a source terminal connected to the ground potential and a gate terminal to which said low power supply voltage is applied.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2018
From: FURUICHI, SHUJI
To: LAPIS SEMICONDUCTOR CO., LTD.
Reel/Frame 045637/0186 →
Priority Claims (1)
JP 2017-087240 · Apr 26, 2017 · national
Continuity (1)
Related Publication 20180316351A1 · Nov 1, 2018
Cited By (1)
US 12,695,380