Source and drain surface treatment for multi-gate field effect transistors
A method includes providing a structure having a substrate and a fin extending from the substrate, wherein the fin includes a first semiconductor material and has a source region, a channel region, and a drain region for a transistor; forming a gate stack over the channel region; performing a surface treatment to the fin in the source and drain regions, thereby converting an outer portion of the fin in the source and drain regions into a different material other than the first semiconductor material; etching the converted outer portion of the fin in the source and drain regions, thereby reducing a width of the fin in the source and drain regions; and depositing an epitaxial layer over the fin in the source and drain regions.
1. A method, comprising:
providing a structure having a substrate and a fin extending from the substrate, wherein the fin includes a first semiconductor material and has a source region, a channel region, and a drain region for a transistor;
forming a gate stack over the channel region;
performing a surface treatment to the fin in the source and drain regions, thereby converting an outer portion of the fin in the source and drain regions into a different material other than the first semiconductor material;
etching the converted outer portion of the fin in the source and drain regions, thereby reducing a width of the fin in the source and drain regions; and
depositing an epitaxial layer over the fin in the source and drain regions, and
wherein the structure further includes an isolation layer covering the substrate and the etching of the converted outer portion also recesses a top surface of the isolation layer.
2. The method of claim 1 , wherein the performing of the surface treatment includes an oxidization process.
3. The method of claim 2 , wherein the oxidization process is a wet oxidization process.
4. The method of claim 1 , wherein the etching of the converted outer portion of the fin also reduces a height of the fin in the source and drain regions.
5. The method of claim 1 , wherein the etching of the converted outer portion of the fin also exposes a portion of the fin in the channel region, and wherein the epitaxial layer is in direct contact with the exposed portion of the fin in the channel region.
6. The method of claim 1 , wherein a bottom portion of the fin is covered by a liner film, and wherein after the etching of the converted outer portion of the fin, a topmost portion of the liner film is higher than the recessed top surface of the isolation layer.
7. The method of claim 1 , wherein the first semiconductor material is silicon germanium.
8. The method of claim 1 , further comprising:
repeating the performing of the surface treatment and the etching of the converted outer portion of the fin until the width of the fin in the source and drain regions is reduced by a predetermined value.
9. The method of claim 1 , before the performing of the surface treatment, further comprising:
forming a spacer over the gate stack and over the fin in the source and drain regions; and
selectively etching the spacer over the fin in the source and drain regions.
10. A method of forming a field effect transistor (FET), comprising:
providing a semiconductor substrate and a fin extending from the semiconductor substrate and through an isolation structure covering the semiconductor substrate, the fin including a first semiconductor material and having a source region, a channel region, and a drain region for the FET;
forming a gate stack over the channel region;
performing an oxidization process on top and sidewall surfaces of the fin in the source and drain regions;
performing an etching process on the oxidized top and sidewall surfaces of the fin in the source and drain regions;
repeating the performing of the oxidization process and the performing of the etching process until a width of the fin in the source and drain regions is reduced by a predetermined value; and
epitaxially growing a material layer covering the fin in the source and drain regions.
11. The method of claim 10 , wherein the etching process includes wet etching.
12. The method of claim 10 , wherein the performing of the etching process also removes a top portion of the isolation structure.
13. The method of claim 12 , wherein a bottom portion of the fin is covered by a liner film, and wherein after the width of the fin in the source and drain regions is reduced by the predetermined value, a portion of the liner film is above the isolation structure.
14. The method of claim 10 , wherein the isolation structure is a shallow trench isolation (STI) feature.
15. The method of claim 10 , wherein a portion of the material layer extends below the gate stack.
16. A method, comprising:
providing a substrate and a fin extending from the substrate and through an isolation structure covering the substrate, wherein the fin includes a source region, a channel region, and a drain region for a transistor;
forming a gate stack over the channel region;
oxidizing top and sidewall surfaces of the fin in the source and drain regions;
etching the oxidized top and sidewall surfaces of the fin to shrink a width and a height of the fin in the source and drain regions, wherein the sidewall surfaces of the fin in the source and drain regions are curved after the etching; and
epitaxially growing a material layer covering the fin in the source and drain regions.
17. The method of claim 16 , wherein a portion of the fin directly under the gate stack is exposed after the etching.
18. The method of claim 16 , wherein a portion of the material layer extends to a region directly under the gate stack.
19. The method of claim 16 , further comprising forming a liner on the sidewall surfaces of the fin, wherein a topmost portion of the liner is below a top surface of the isolation structure after the etching.
20. The method of claim 16 , wherein etching the oxidized top and sidewall surfaces of the fin further includes etching the isolation structure to thereby recess the isolation structure.