Low dropout regulator with a controlled startup
View Patent ↗A low dropout voltage regulator incorporates an N-channel MOS pass transistor, a main error amplifier, a first buffer circuit, an auxiliary error amplifier, a second buffer circuit, and a decision circuit. The auxiliary error amplifier consumes less bias current. In one embodiment, the decision circuit compares the portion of the output voltage with a bias voltage to control the gate of the N-channel MOS pass transistor, wherein the value of the bias voltage is less than the value of the reference voltage.
1. A low dropout voltage regulator, comprising:
an N-channel MOS pass transistor having a drain coupled to receive an input voltage and a source coupled to generate an output voltage;
a main error amplifier having a positive input coupled to receive a portion of the output voltage, a negative input coupled to receive a reference voltage, and an amplifier output;
a first buffer circuit coupled between the amplifier output of the main error amplifier and a gate of the N-channel MOS pass transistor;
an auxiliary error amplifier which consumes less bias current than the main error amplifier, the auxiliary error amplifier having a first positive input coupled to receive the portion of the output voltage, a second positive input, a negative input coupled to receive the reference voltage, and an amplifier output;
a second buffer circuit coupled between the amplifier output of the auxiliary error amplifier and the gate of the N-channel MOS pass transistor; and
a decision circuit configured to compare the portion of the output voltage with a bias voltage to control the gate of the N-channel MOS pass transistor;
wherein a value of the bias voltage is less than the value of the reference voltage.
2. The low dropout voltage regulator of claim 1 , wherein the first buffer circuit comprises:
a P-channel MOS transistor, having a source coupled to the gate of the N-channel MOS pass transistor, a gate coupled to the amplifier output of the main error amplifier, and a drain coupled to a ground terminal; and
a current source coupled to the source of the P-channel MOS transistor.
3. The low dropout voltage regulator of claim 1 , wherein the second buffer circuit comprises:
a first output stage having an input coupled to the amplifier output of the auxiliary error amplifier, and an output coupled to the amplifier output of the main error amplifier; and
a second output stage, having an input coupled to the amplifier output of the auxiliary error amplifier, and an output coupled to the gate of the N-channel MOS pass transistor.
4. The low dropout voltage regulator of claim 3 , wherein the first output stage comprises:
a first N-channel MOS transistor having a gate coupled to the amplifier output of the auxiliary error amplifier, a drain coupled to the amplifier output of the main error amplifier, and a source coupled to the ground terminal.
5. The low dropout voltage regulator of claim 3 , wherein the second output stage comprises:
a second N-channel MOS transistor, having a gate coupled to the amplifier output of the auxiliary error amplifier, a drain coupled to the gate of the N-channel MOS pass transistor, and a source coupled to the ground terminal; and
a capacitor coupled between the gate of the N-channel MOS pass transistor and the gate of the second N-channel MOS transistor.
6. The low dropout voltage regulator of claim 1 , wherein the decision circuit comprises:
a comparator configured to compare the portion of the output voltage with the bias voltage to generate a comparison signal; and
an output stage having an input coupled to receive the comparison signal and an output coupled to the second positive input of the auxiliary error amplifier.
7. The low dropout voltage regulator of claim 6 , wherein the output stage of the decision circuit comprises:
an N-channel MOS transistor having a gate coupled to receive the comparison signal, a drain coupled to the second positive input of the auxiliary error amplifier;
a capacitor coupled the drain of the N-channel MOS transistor; and
a current source coupled to a source of the N-channel MOS transistor.
8. The low dropout voltage regulator of claim 1 , wherein during a startup phase, the reference voltage is reset and then rises according to a predetermined ramp; when the portion of the output voltage is less than the bias voltage, the auxiliary error amplifier, the second buffer circuit, and the N-channel MOS pass transistor constitute a first negative feedback loop which forces the portion of the output voltage and the reference voltage to be substantially equal.
9. The low dropout voltage regulator of claim 8 , wherein when the portion of the output voltage is larger than the bias voltage, the main error amplifier, the first buffer circuit, and the N-channel MOS pass transistor constitute a second negative feedback loop which forces the portion of the output voltage and the reference voltage to be substantially equal.
10. The low dropout voltage regulator of claim 9 , wherein when the portion of the output voltage rises close to the bias voltage, the decision circuit sends a first signal falling in a fixed rate to the second positive input of the auxiliary error amplifier and when the first signal is less than the portion of the output voltage, the second negative feedback loop activates and the first negative feedback loop deactivates.