Methods of forming semiconductor packages with back side metal
Implementations of a method of forming semiconductor packages may include: providing a wafer having a plurality of devices, etching one or more trenches on a first side of the wafer between each of the plurality of devices, applying a molding compound to the first side of the wafer to fill the one or more trenches; grinding a second side of the wafer to a desired thickness, and exposing the molding compound included in the one or more trenches. The method may include etching the second side of the wafer to expose a height of the molding compound forming one or more steps extending from the wafer, applying a back metallization to a second side of the wafer, and singulating the wafer at the one or more steps to form a plurality of semiconductor packages. The one or more steps may extend from a base of the back metallization.
1. A method of forming a semiconductor package, the method comprising:
providing a wafer comprising a plurality of devices;
etching one or more trenches on a first side of the wafer between each of the plurality of devices;
applying a molding compound to the first side of the wafer, wherein the molding compound fills the one or more trenches;
grinding a second side of the wafer to a desired thickness and exposing the molding compound comprised in the one or more trenches;
etching the second side of the wafer to expose a height of the molding compound, wherein one or more steps are formed extending from the wafer;
applying a back metallization to a second side of the wafer, wherein portions of the back metallization over the one or more steps extend beyond a base of the back metallization; and
singulating the wafer at the one or more steps to form a plurality of semiconductor packages.
2. The method of claim 1 , further comprising using the portions of the back metallization over the one or more steps to align the wafer while singulating the wafer.
3. The method of claim 1 , further comprising grinding the first side of the wafer to expose one or more bumps comprised in the plurality of devices.
4. The method of claim 1 , wherein applying the molding compound comprises compression molding.
5. The method of claim 1 , wherein applying the molding compound comprises one of printing and spin coating.
6. The method of claim 1 , wherein etching the second side of the wafer comprises dry etching.
7. The method of claim 1 , wherein the one or more steps comprise a width of 50 to 100 microns.
8. The method of claim 1 , wherein the one or more steps comprise a height of 3 to 10 microns.
9. The method of claim 1 , wherein the back metallization comprises sputtered Ti/Cu.
10. The method of claim 1 , wherein the back metallization comprises one of copper plating, nickel plating, gold plating, tin/silver plating, and any combination thereof.
11. The method of claim 1 , wherein singulating the plurality of semiconductor packages comprises sawing.
12. A method of forming a semiconductor package, the method comprising:
providing a silicon wafer comprising a plurality of devices;
etching one or more trenches on a first side of the silicon wafer between each of the plurality of devices;
applying a molding compound to the first side of the silicon wafer, wherein the molding compound fills the one or more trenches;
grinding a second side of the silicon wafer to a desired thickness and exposing the molding compound comprised in the one or more trenches;
etching the second side of the silicon wafer to expose a height of the molding compound, wherein one or more steps are formed extending from the silicon wafer;
applying a back metallization to a second side of the silicon wafer, wherein portions of the back metallization over the one or more steps extend beyond a base of the back metallization; and
singulating the silicon wafer at the one or more steps to form a plurality of semiconductor packages.
13. The method of claim 12 , further comprising using the portion of the back metallization over the one or more steps to align the silicon wafer while singulating the wafer.
14. The method of claim 12 , further comprising grinding the first side of the silicon wafer to expose one or more bumps comprised in the plurality of devices.
15. The method of claim 12 , wherein applying the molding compound comprises compression molding.
16. The method of claim 12 , wherein applying the molding compound comprises one of printing and spin coating.
17. The method of claim 12 , wherein etching the second side of the wafer comprises dry etching.
18. The method of claim 12 , wherein the one or more steps comprise a width of 50 to 100 microns.
19. The method of claim 12 , wherein the one or more steps comprise a height of 3 to 10 microns.
20. The method of claim 12 , wherein the back metallization comprises sputtered Ti/Cu.
21. The method of claim 12 , wherein the back metallization comprises one of copper plating, nickel plating, gold plating, tin/silver plating, and any combination thereof.