Hardware secure element, related processing system, integrated circuit, device and method

1. A hardware secure element comprising:

a microprocessor;

a memory having stored thereon a plurality of software routines executable by said microprocessor, wherein each software routine starts at a respective memory start address;

a receiver circuit configured to receive command data including a command; and

hardware message handler circuitry configured to:

determine a software routine to be executed by said microprocessor as a function of said command; and

provide address data to said microprocessor indicating said software routine to be executed, wherein

said memory has stored thereon a look-up table starting at a look-up table memory start address, wherein elements of said look-up table contain the memory start addresses of said software routines, and wherein said hardware message handler circuitry has associated a configuration register containing the look-up table memory start address;

said hardware message handler circuitry is configured to determine a memory address of an element of said look-up table as a function of said look-up table memory start address and said command;

said hardware message handler circuitry is configured to provide said memory address of said element of said look-up table to said microprocessor; and

said microprocessor is configured to:

read a jump address from said memory at said memory address provided by said hardware message handler circuitry; and

perform a jump to the jump address read from said memory address provided by said hardware message handler circuitry.

2. The hardware secure element according to claim 1 , wherein said software routines comprise:

a plurality of command handlers having software instructions to perform operations using a secret key, said operations including an encryption operation using a first cipher key and a decryption operation using a second cipher key.

3. The hardware secure element according to claim 1 , wherein said software routines include one or more error handlers, wherein said hardware message handler circuitry is configured to:

determine whether an error occurred; and

in case an error occurred, provide data indicating said software routine to be executed to said microprocessor indicating that one of said one or more error handlers should be executed.

4. The hardware secure element according to claim 1 , wherein said command data received includes, in addition to said command, a parameter field, the parameter field including one or more parameters, wherein said hardware secure element includes a parameter check circuit configured to:

verify whether said one or more parameters are correct; and

in case said one or more parameters are not correct, generate a parameter error flag.

5. The hardware secure element according to claim 4 , wherein said one or more error handlers include a first error handler and a second error handler, wherein said receiver circuit is arranged to provide a reception status signal that indicates whether a transmission error occurred, and wherein said hardware message handler circuitry is configured to:

in case said reception status signal indicates that a transmission error occurred, provide first error data to said microprocessor indicating that said first error handler should be executed; and

in case said parameter error flag indicates that a transmission error occurred, provide second error data to said microprocessor indicating that said second error handler should be executed.

6. A hardware secure element, comprising:

a microprocessor;

a memory having stored thereon a plurality of software routines executable by said microprocessor, wherein each software routine starts at a respective memory start address;

a receiver circuit configured to receive command data including a command; and

hardware message handler circuitry configured to:

determine a software routine to be executed by said microprocessor as a function of said command; and

provide address data to said microprocessor indicating said software routine to be executed, wherein

said software routines comprise a plurality of command handlers having software instructions to perform operations using a secret key, said operations including an encryption operation using a first cipher key and a decryption operation using a second cipher key; and

said software routines include a default handler, wherein said hardware message handler circuitry is configured to:

determine whether a value representing said command is greater than a total number of said plurality of command handlers; and

in case said value of said command is greater than the total number of said plurality of command handlers, provide data to said microprocessor indicating that said default handler should be executed.

7. The hardware secure element according to claim 6 , wherein said memory has stored thereon a look-up table starting at a look-up table memory start address, wherein elements of said look-up table contain the memory start addresses of said software routines, and wherein said hardware message handler circuitry has associated a configuration register containing the look-up table memory start address.

8. The hardware secure element according to claim 7 , wherein said hardware message handler circuitry is configured to determine a memory address of an element of said look-up table as a function of said look-up table memory start address and said command.

9. The hardware secure element according to claim 8 , wherein said hardware message handler circuitry is configured to provide said memory address of said element of said look-up table to said microprocessor, and wherein said microprocessor is configured to:

read a jump address from said memory at said memory address provided by said hardware message handler circuitry; and

perform a jump to the jump address read from said memory address provided by said hardware message handler circuitry.

10. The hardware secure element according to claim 8 , wherein said hardware message handler circuitry is configured to:

read a jump address from said memory at said memory address of said element of said look-up table; and

provide the jump address read from said memory address of said element of said look-up table to said microprocessor, wherein said microprocessor is configured to perform a jump to the jump address provided by said hardware message handler circuitry.

11. The hardware secure element according to claim 6 , wherein said hardware message handler circuitry has associated a configuration register arranged to store the total number of said plurality of command handlers.

12. A processing system comprising:

a hardware secure element, the hardware secure element including:

a microprocessor;

a memory having stored thereon a plurality of software routines executable by said microprocessor, wherein each software routine starts at a respective memory start address;

a receiver circuit configured to receive command data including a command; and

hardware message handler circuit configured to:

determine a software routine to be executed by said microprocessor as a function of said command; and

provide address data to said microprocessor indicating said software routine to be executed;

a transmitter circuit configured to transmit data to the receiver circuit of said hardware secure element; and

first processing circuitry configured with no direct access to the memory of said hardware secure element, wherein said first processing circuitry is configured to transmit, via said transmitter circuit, a command to said hardware secure element, wherein

said software routines comprise a plurality of command handlers having software instructions to perform operations using a secret key, said operations including an encryption operation using a first cipher key and a decryption operation using a second cipher key, and

said software routines include a default handler, wherein said hardware message handler circuitry is configured to:

determine whether a value representing said command is greater than a total number of said plurality of command handlers; and

in case said value of said command is greater than the total number of said plurality of command handlers, provide data to said microprocessor indicating that said default handler should be executed.

13. The processing system of claim 12 , wherein said hardware secure element is arranged within an integrated circuit.

14. The processing system of claim 12 , comprising:

a second hardware secure element;

a second transmitter circuit;

second processing circuitry communicatively coupled to the second transmitter and the second hardware secure element; and

a communication system, the communication system arranged to exchange data between the first processing circuitry and the second processing circuitry.

15. The processing system of claim 14 , wherein said processing system is integrated in a vehicle.

16. A method to operate a hardware secure element, comprising:

storing a plurality of software routines in a memory;

providing configuration information to a hardware message handler circuit via a microprocessor, said configuration information indicative of said plurality of software routines stored in said memory;

receiving first data via a receiver circuit, said first data including a command;

determining, via said hardware message handler circuit, which software routine of said plurality of software routines is to be executed by said microprocessor as a function of said command; and

sending to said microprocessor from said hardware message handler circuit, second data indicating which software routine of said plurality of software routines is to be executed, wherein

said software routines comprise a plurality of command handlers having software instructions to perform operations using a secret key, said operations including an encryption operation using a first cipher key and a decryption operation using a second cipher key, and

said software routines include a default handler, wherein said hardware message handler circuit is configured to:

determine whether a value representing said command is greater than a total number of said plurality of command handlers; and

in case said value of said command is greater than the total number of said plurality of command handlers, provide data to said microprocessor indicating that said default handler should be executed.

17. The method to operate the hardware secure element of claim 16 , wherein determining, via said hardware message handler circuit, which software routine of said plurality of software routines is to be executed by said microprocessor as the function of said command comprises:

providing address data to said microprocessor indicating which software routine of said plurality of software routines is to be executed by said microprocessor.

18. The method to operate the hardware secure element of claim 16 , comprising:

storing a start address of a look-up table in a configuration register; and

retrieving a software routine start address indicating which software routine of said plurality of software routines is to be executed by said microprocessor as the function of said command; and

providing to said microprocessor the software routine start address indicating which software routine of said plurality of software routines is to be executed by said microprocessor.

19. The method to operate the hardware secure element of claim 16 , comprising:

reading a jump address from said memory; and

providing the jump address read from said memory to said microprocessor, wherein said microprocessor is configured to perform a jump to the jump address.

20. The method to operate the hardware secure element of claim 16 , comprising:

determining whether an error occurred; and

in case an error occurred, providing data indicating an error handler to be executed by said microprocessor.

21. A processing system comprising:

a hardware secure element, the hardware secure element including:

a microprocessor;

a memory having stored thereon a plurality of software routines executable by said microprocessor, wherein each software routine starts at a respective memory start address;

a receiver circuit configured to receive command data including a command; and

a hardware message handler circuit configured to:

a) determine a software routine to be executed by said microprocessor as a function of said command; and

b) provide address data to said microprocessor indicating said software routine to be executed;

a transmitter circuit configured to transmit data to the receiver circuit of said hardware secure element; and

first processing circuitry configured with no direct access to the memory of said hardware secure element, wherein said first processing circuitry is configured to transmit, via said transmitter circuit, a command to said hardware secure element,

wherein,

said memory has stored thereon a look-up table starting at a look-up table memory start address, wherein elements of said look-up table contain the memory start addresses of said software routines, and wherein said hardware message handler circuitry has associated a configuration register containing the look-up table memory start address;

said hardware message handler circuit is configured to determine a memory address of an element of said look-up table as a function of said look-up table memory start address and said command;

said hardware message handler circuit is configured to provide said memory address of said element of said look-up table to said microprocessor; and

said microprocessor is configured to:

read a jump address from said memory at said memory address provided by said hardware message handler circuitry; and

perform a jump to the jump address read from said memory address provided by said hardware message handler circuitry.

22. The processing system of claim 21 , wherein said hardware secure element is arranged within an integrated circuit.

23. The processing system of claim 21 , wherein said processing system is integrated in a vehicle.

24. A method to operate a hardware secure element, comprising:

storing a plurality of software routines in a memory;

providing configuration information to a hardware message handler circuit via a microprocessor, said configuration information indicative of said plurality of software routines stored in said memory;

receiving first data via a receiver circuit, said first data including a command;

determining, via said hardware message handler circuit, which software routine of said plurality of software routines is to be executed by said microprocessor as a function of said command; and

sending to said microprocessor from said hardware message handler circuit, second data indicating which software routine of said plurality of software routines is to be executed, wherein

said memory has stored thereon a look-up table starting at a look-up table memory start address, wherein elements of said look-up table contain memory start addresses of said software routines, and wherein said hardware message handler circuitry has associated a configuration register containing the look-up table memory start address;

said hardware message handler circuit is configured to determine a memory address of an element of said look-up table as a function of said look-up table memory start address and said command;

said hardware message handler circuitry is configured to provide said memory address of said element of said look-up table to said microprocessor; and

said microprocessor is configured to:

read a jump address from said memory at said memory address provided by said hardware message handler circuit; and

perform a jump to the jump address read from said memory address provided by said hardware message handler circuit.

25. The method to operate the hardware secure element of claim 24 , comprising:

performing operations of at least one of the plurality of software routines using a secret key, said operations including an encryption operation using a first cipher key and a decryption operation using a second cipher key.

26. The method to operate the hardware secure element of claim 24 , comprising:

determining whether an error occurred; and

in case an error occurred, providing data indicating an error handler to be executed by said microprocessor.