Enhanced self-alignment of vias for a semiconductor device
A method of forming a self-aligned pattern of vias in a semiconductor device comprises etching a pattern of lines that contain notches that are narrower than other parts of the line. Thereafter, vias are created where the notches are located. The locations of the vias are such that the effect of blown-out areas is minimized. Thereafter, the lines are etched and the vias and line areas are filled. The layers are planarized such that the metal fill is level with a surrounding ultra-low-k dielectric. Additional metal layers, lines, and vias can be created. Other embodiments are also described herein.
1. An integrated circuit comprising:
metal lines formed to have one or more notched areas, wherein the metal lines comprise adjacent metal lines; and
metal vias formed in the one or more notched areas such that the metal vias in the adjacent metal lines are offset from one another, a portion of one of the metal vias being bounded in a lateral direction by a first part of a dielectric layer and a second part of the dielectric layer;
wherein a metal layer is under and in direct contact with the one of the metal vias such that an entire bottom part of the portion in the lateral direction of the one of the metal vias bounded between the first part of the dielectric layer and the second part of the dielectric layer is directly formed on a top surface of the metal layer.
2. The integrated circuit of claim 1 , wherein the one or more notched areas are smaller than the metal lines.
3. The integrated circuit of claim 1 , wherein the one or more notched areas have a reduced size in the metal lines.
4. The integrated circuit of claim 1 , wherein the dielectric layer separates the metal lines from the metal layer underneath.
5. The integrated circuit of claim 1 , wherein material of the metal lines next to one of the metal vias does not contact the metal layer under the metal lines, and the material is on an opposite side of the dielectric layer from the one of the metal vias.
6. The integrated circuit of claim 1 , wherein no intervening layer is between the portion of the one of the metal vias and the metal layer underneath.