Permuting in a matrix-vector processor

1. A circuit comprising:

an input register configured to receive an input vector of input elements;

a control register configured to receive a control vector of control elements, wherein each control element of the control vector corresponds to a respective input element of the input vector, and wherein each control element of the control vector specifies a permutation of a corresponding input element of the input vector, the permutation specifying a number of positions to rotate the corresponding input element of the input vector; and

a permute execution circuit configured to generate an output vector of output elements corresponding to a permutation of the input vector, wherein generating each output element of the output vector comprises:

accessing, at a particular position of the input register, a particular input element of the input vector;

accessing, at the control register, a particular control element of the control vector corresponding to the particular input element of the input vector;

selecting a particular position of the output vector based on (i) the particular position of the particular input element in the input register and (ii) a number of positions to rotate the particular element of the input vector specified by the particular control element of the control vector; and

outputting the particular input element of the input vector as an output element at the particular position of the output vector.

2. The circuit of claim 1 , comprising an output register configured to receive the output vector.

3. The circuit of claim 2 , wherein the output register is configured to output the output vector as a staggered output such that a single output element of the output vector is output at each cycle in an order beginning with a lowest-order bit position of the output vector.

4. The circuit of claim 1 , wherein the input vector is received as a staggered input such that each input element of the input vector is received at each cycle in an order beginning with a lowest-order bit position of the input vector.

5. The circuit of claim 4 , wherein receiving the input vector as a staggered input comprises:

receiving, at a flattening register, each input element of the input vector in a separate cycle in an order beginning with a lowest-order bit position of the flattening register; and

popping all input elements of the input vector simultaneously from the flattening register to the input register.

6. The circuit of claim 5 , wherein popping all input elements of the input vector simultaneously from the flattening register to the input register comprises:

determining that a highest-order bit of the flattening register has received valid data corresponding to a highest-order bit of the input vector; and

popping all input elements of the input vector simultaneously from the flattening register to the input register in response to determining that the highest-order bit of the flattening register has received valid data corresponding to the highest-order bit of the input vector.

7. The circuit of claim 5 , wherein popping all input elements of the input vector simultaneously from the flattening register to the input register comprises:

determining that the flattening register has received a number of input elements of the input vector equal to a dimension of the input vector; and

popping all input elements of the input vector simultaneously from the flattening register to the input register in response to determining that the flattening register has received the number of input elements of the input vector equal to the dimension of the input vector.

8. The circuit of claim 1 , wherein the control vector is received from an off-chip processor that is separate from the circuit.

9. The circuit of claim 1 , wherein the permute execution circuit comprises a memory crossbar.

10. The circuit of claim 1 , wherein the permute execution circuit comprises multiple one-to-many multiplexors, and wherein an output of each one-to-many multiplexor of the permute execution circuit is controlled by a corresponding control element of the control vector.

11. The circuit of claim 1 , wherein the input vector of input elements corresponds to a row of an input matrix or a column of an input matrix.

12. The circuit of claim 1 , wherein the number of positions to rotate the particular element of the input vector specified by the particular control element of the control vector is a number of positions to rotate the particular element of the input vector in a particular direction.

13. A circuit for permuting an input matrix, the circuit comprising:

an input register configured to receive an input vector of input elements that corresponds to a vector included in the input matrix;

a control register configured to receive a control vector of control elements, wherein each control element of the control vector corresponds to a respective input element of the input vector, and wherein each control element of the control vector specifies a permutation of a corresponding input element of the input vector, the permutation specifying a number of positions to rotate the corresponding input element of the input vector; and

a permute execution circuit that is configured to generate an output vector of output elements corresponding to a permutation of the input vector, wherein generating each output element of the output vector comprises:

accessing, at a particular position of the input register, a particular input element of the input vector;

accessing, at the control register, a particular control element of the control vector corresponding to the particular input element of the input vector;

selecting a particular position of the output vector based on (i) the particular position of the particular input element in the input register and (ii) a number of positions to rotate the particular element of the input vector specified by the particular control element of the control vector; and

outputting the particular input element of the input vector as an output element at the particular position of the output vector.

14. The circuit of claim 13 , wherein selecting the particular position of the output vector based on (i) the particular position of the particular input element in the input register and (ii) the number of positions to rotate the particular element of the input vector specified by the particular control element of the control vector comprises:

selecting a position of the output vector that is the number of positions specified by the particular control element of the control vector from the particular position of the particular input element in the input register.

15. A circuit comprising:

an input register configured to receive an input vector of input elements;

a control register configured to receive a control vector of control elements, wherein each control element of the control vector corresponds to a respective input element of the input vector, and wherein each control element of the control vector is a pointer specifying a position of an output register to which the respective input element of the input vector is to be output; and

a permute execution circuit configured to generate an output vector of output elements corresponding to a permutation of the input vector, wherein generating each output element of the output vector comprises:

accessing, at a particular position of the input register, a particular input element of the input vector;

accessing, at the control register, a particular control element of the control vector corresponding to the particular input element of the input vector, wherein the particular control element of the control vector is a particular pointer specifying a particular position of the output register to which the particular input element of the input vector is to be output;

selecting a particular position of the output vector based at least on the particular control element of the control vector; and

outputting the particular input element of the input vector as an output element at the particular position of the output vector.

16. The circuit of claim 15 , wherein outputting the particular input element of the input vector as an output element at the particular position of the output vector comprises:

outputting the particular input element of the input vector as an output element at the particular position of the output register that is specified by the particular pointer.