Delay circuitry to hold up power to a mass storage device and method therefor
A delay circuitry is configured to hold up power to a mass storage device after a power fault disables communication of the mass storage device with the host computer. The time delay is sufficient to allow saving of in-flight data from the storage device's volatile cache to the non-volatile media (of the storage device) and to update a metadata table in the non-volatile media.
1. A computer device, comprising:
an enclosure having one or more host devices powered by a power supply;
a plurality of non-volatile memory mass storage devices having a volatile memory cache and a non-volatile memory data carrier;
a plurality of interposer boards, the one or more host devices communicatively coupled to the plurality of non-volatile memory mass storage devices by the plurality of interposer boards;
where at least one of the host devices in the one or more host devices is configured to exchange data and control signals with selected non-volatile memory devices in the plurality of non-volatile memory mass storage devices; and
where each of the interposer boards in the plurality of interposer boards comprises:
a first e-fuse to gate power to a logic circuit on the at least one interposer board along a data path to a first non-volatile memory mass storage device in the plurality of non-volatile memory mass storage devices;
a second e-fuse to gate power to the first non-volatile memory mass storage device in the plurality of non-volatile memory mass storage devices, wherein the first and the second e-fuses are logically connected to fault the second e-fuse when a fault condition occurs on the first e-fuse; and
a delay circuit, coupled between the first e-fuse and the second e-fuse, configured to delay the fault of the second e-fuse after the fault of the first e-fuse.
2. The computer device of claim 1 , wherein the fault of the second e-fuse causes power to be turned Off to the first non-volatile memory mass storage device after a time delay caused by the delay circuit, the time delay relative to the fault of the first e-fuse.
3. The computer device of claim 2 , wherein the time delay provides sufficient time for data to be copied from the volatile cache memory in the first non-volatile memory mass storage device to the non-volatile memory data carrier.
4. The computer device of claim 1 , further comprising:
a multiplexing control logic circuit on the interposer boards, the multiplexing logic configured to select a non-volatile mass storage device in the plurality of non-volatile memory devices by the one or more host devices, where a power converter powers the multiplexing control logic circuit.
5. The computer device of claim 4 , wherein the delay circuit comprises:
an array of capacitors having one or more capacitors;
a supply voltage adapted to charge the one or more capacitors in the array of capacitors;
a first metal-oxide-semiconductor field-effect transistor (MOSFET) connected to the array of capacitors, wherein when in a non-fault condition, the first MOSFET is in a low-resistance state to connect the supply voltage to the one or more capacitors in the array of capacitors to a ground; and when a fault condition from the power converter powering the multiplexing logic circuit and connected to a gate of the first MOSFET switches the first MOSFET to a high resistance state to ground, the high resistance state of the first MOSFET preventing the supply voltage to the array of capacitors from draining to ground and causing charging of the array of capacitors; and
a second MOSFET coupled to the array of capacitors, wherein when a charge of the one or more capacitors in the array of capacitors exceeds a gate threshold voltage of the second MOSFET, the second MOSFET switches from a high resistance state to a low resistance state, and the low resistance state of the second MOSFET causes the second e-fuse to turn Off power to the first non-volatile memory mass storage device.
6. The computer device of claim 5 , further comprising a first resistor coupled between the supply voltage and the array of capacitors for limiting an inrush current; and a second resistor coupled between the array of capacitors and the first MOSFET for limiting a drain of the first MOSFET to ground.
7. The computer device of claim 5 , wherein the second e-fuse includes a sense resistor for sensing an over current condition on the first non-volatile memory mass storage device.
8. The computer device of claim 5 , wherein the supply voltage is 12 volts.
9. The computer device of claim 5 , wherein the power converter provides a voltage of 3.3 volts or 1.8 volts.
10. The computer device of claim 1 , wherein the non-volatile memory mass storage devices include non-volatile memory express (NVMe) devices and/or peripheral component interconnect express (PCIe) devices.
11. A circuit, comprising:
a non-volatile memory mass storage device having a volatile memory device and non-volatile memory data carrier, the volatile memory device configured to cache data prior to storing the data on the non-volatile memory data carrier;
a power supply providing power, along a first power path, to a logic circuit along a data path to the storage device, and along a second power path to the storage device;
a power fault detection circuit adapted to remove power from the second power path when a power fault is detected along the first power path; and
a delay circuit configured to delay shutting off the non-volatile memory mass storage device after detection of the power fault along the first power path, the delay circuit providing time for the data to be copied from the volatile memory device to the non-volatile memory data carrier, wherein the delay circuit comprises:
an array of capacitors having one or more capacitors;
a supply voltage adapted to charge the one or more capacitors in the array of capacitors;
a first metal-oxide-semiconductor field-effect transistor (MOSFET) connected to the array of capacitors, wherein when in a non-fault condition, the first MOSFET is in a low-resistance state to connect the supply voltage to the one or more capacitors in the array of capacitors to a ground; and when a fault condition from the power converter powering the multiplexing logic circuit and connected to a gate of the first MOSFET switches the first MOSFET to a high resistance state to ground, the high resistance state of the first MOSFET preventing the supply voltage to the array of capacitors from draining to the ground and causing charging of the array of capacitors; and
a second MOSFET coupled to the array of capacitors, wherein when a charge of the one or more capacitors in the array of capacitors exceeds a gate threshold voltage of the second MOSFET, the second MOSFET switches from a high resistance state to a low resistance state, and the low resistance state of the second MOSFET causes the second e-fuse to turn Off power to the non-volatile memory mass storage device.
12. The circuit of claim 11 , further comprising a first resistor coupled between the supply voltage and the array of capacitors for limiting an inrush current; and wherein a second resistor coupled between the array of capacitors and the first MOSFET for limiting a drain of the first MOSFET to the ground.
13. A computer device, comprising:
an enclosure having one or more host devices powered by a power supply;
a plurality of non-volatile memory mass storage devices;
a plurality of interposer boards, the one or more host devices communicatively coupled to the plurality of non-volatile memory mass storage devices by the plurality of interposer boards;
a midplane coupled between the one or more host devices and the plurality of interposer boards;
where at least one of the host devices in the one or more host devices is configured to exchange data and control signals with selected non-volatile memory mass storage devices in the plurality of non-volatile memory mass storage devices; and
where each of the interposer boards in the plurality of interposer boards comprises:
a first e-fuse to gate power to a logic circuit on the at least one interposer board along a data path to a first non-volatile memory mass storage device in the plurality of non-volatile memory mass storage devices;
a second e-fuse to gate power to the first non-volatile memory mass storage device in the plurality of non-volatile memory mass storage devices, wherein the first and the second e-fuses are logically connected to fault the second e-fuse when a fault condition occurs on the first e-fuse; and
a delay circuit, coupled between the first e-fuse and the second e-fuse, configured to delay the fault of the second e-fuse after the fault of the first e-fuse; and
where the midplane receives the data and the control signals from the one or more host devices and routes the data and the control signals to the plurality of interposer boards.
14. The computer device of claim 13 , wherein the delay circuit comprises:
an array of capacitors having one or more capacitors;
a midplane supply voltage source adapted to charge the one or more capacitors in the array of capacitors;
a first metal-oxide-semiconductor field-effect transistor (MOSFET) connected to the array of capacitors, wherein in a non-fault condition, the first MOSFET is in a low-resistance state to connect the midplane supply voltage source to the one or more capacitors in the array of capacitors to a ground and wherein a fault condition from the power converter powering the multiplexing logic circuit and connected to a gate of the first MOSFET switches the first MOSFET to a high resistance state to ground, the high resistance state of the first MOSFET prevents the supply voltage to the array of capacitors from draining to the ground and causing charging of the array of capacitors; and
a second MOSFET coupled to the array of capacitors, when a charge of the one or more capacitors in the array of capacitors exceeds a gate threshold voltage of the second MOSFET the second MOSFET switches from a high resistance state to a low resistance state, and the low resistance state of the second MOSFET causes the second e-fuse to turn Off power to the plurality of non-volatile memory mass storage device.
15. The computer device of claim 14 , further comprising a first resistor coupled between the midplane supply voltage and the array of capacitors for limiting an inrush current; and a second resistor coupled between the array of capacitors and the first MOSFET for limiting a drain of the first MOSFET to the ground.
16. The computer device of claim 14 , wherein the second e-fuse includes a sense resistor for sensing an over current condition on the first non-volatile memory mass storage device.