IP Library › Granted Patent US 10,680,652
Granted Patent B2
US 10,680,652 · App. 15/971,877 · Granted Jun 9, 2020

Method and apparatus for channel encoding and decoding in communication or broadcasting system

Inventors: Seokki Ahn (Suwon-si, KR); Kyungjoong Kim (Suwon-si, KR); Seho Myung (Seoul, KR); Hongsil Jeong (Suwon-si, KR); Min Jang (Seongnam-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H03M13/255H03M13/036H03M13/116H03M13/1111H03M13/1188H03M13/2906H03M13/618H03M13/6356H03M13/6393H03M13/6516H04L1/0009H04L1/0041H04L1/0045H04L1/0057H04L1/0068H04L1/0075H03M13/09
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Quick Facts
Patent No.
US 10,680,652
App. No.
15/971,877
Granted
Jun 9, 2020
Kind
B2
Abstract

The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). A channel encoding method in a communication or broadcasting system includes identifying an input bit size, determining a block size (Z), determining an LDPC sequence for LDPC encoding, and performing the LDPC encoding based on the LDPC sequence and the block size.

Claims (222)

1. A channel encoding method performed by a transmitter in a communication system, the method comprising:

identifying a bit sequence to which low density parity check (LDPC) encoding is to be applied;

obtaining a first matrix based on first information and second information, wherein the first matrix consists of matrices of size Z×Z;

obtaining an encoded bit sequence by performing the LDPC encoding on the bit sequence based on the first matrix; and

transmitting the encoded bit sequence to a receiver,

wherein the first information indicates position information on non-zero matrices among the matrices of size Z×Z in the first matrix,

wherein the second information indicates information on shift values for the non-zero matrices, and

wherein the first information includes thirty-two rows corresponding to a sequence given below:

0 1 2 3 6 9 10 11

0 3 4 5 6 7 8 9 11 12

0 1 3 4 8 10 12 13

1 2 4 5 6 7 8 9 10 13

0 1 11 14

0 1 5 7 11 15

0 5 7 9 11 16

1 5 7 11 13 17

0 1 12 18

1 8 10 11 19

0 1 6 7 20

0 7 9 13 21

1 3 11 22

0 1 8 13 23

1 6 11 13 24

0 10 11 25

1 9 11 12 26

1 5 11 12 27

0 6 7 28

0 1 10 29

1 4 11 30

0 8 13 31

1 2 32

0 3 5 33

1 2 9 34

0 5 35

2 7 12 13 36

0 6 37

1 2 5 38

0 4 39

2 5 7 9 40

1 13 41.

2. The method of claim 1 , further comprising:

determining the size Z of the matrices, based on a size of the bit sequence.

3. The method of claim 2 , wherein the size Z is determined as one of values given below:

Z1′={3, 6, 12, 24, 48, 96, 192, 384}

Z2′={11, 22, 44, 88, 176, 352}

Z3′={5, 10, 20, 40, 80, 160, 320}

Z4′={9, 18, 36, 72, 144, 288}

Z5′={2, 4, 8, 16, 32, 64, 128, 256}

Z6′={15, 30, 60, 120, 240}

Z7′={7, 14, 28, 56, 112, 224}

Z8′={13, 26, 52, 104, 208}.

4. The method of claim 2 , wherein the obtaining the first matrix further comprises:

performing a modulo operation between the size Z and a shift value for each of the non-zero matrices associated with the second information; and

obtaining the each of the non-zero matrices that is a circulant permutation matrix based on a result of the modulo operation.

5. The method of claim 1 , wherein the first information is capable of indicating positions of the non-zero matrices of up to 42 rows and 52 columns.

6. A channel decoding method performed by a receiver in a communication system, the method comprising:

receiving a signal from a transmitter;

obtaining a first matrix based on first information and second information, wherein the first matrix consists of matrices of size Z×Z;

performing low density parity check (LDPC) decoding on a first sequence corresponding to the received signal based on the first matrix; and

obtaining a second bit sequence by the LDPC decoding,

wherein the first information indicates position information on non-zero matrices among the matrices of size Z×Z in the first matrix,

wherein the second information indicates information on shift values for the non-zero matrices, and

wherein the first information includes thirty-two rows corresponding to a sequence given below:

0 1 2 3 6 9 10 11

0 3 4 5 6 7 8 9 11 12

0 1 3 4 8 10 12 13

1 2 4 5 6 7 8 9 10 13

0 1 11 14

0 1 5 7 11 15

0 5 7 9 11 16

1 5 7 11 13 17

0 1 12 18

1 8 10 11 19

0 1 6 7 20

0 7 9 13 21

1 3 11 22

0 1 8 13 23

1 6 11 13 24

0 10 11 25

1 9 11 12 26

1 5 11 12 27

0 6 7 28

0 1 10 29

1 4 11 30

0 8 13 31

1 2 32

0 3 5 33

1 2 9 34

0 5 35

2 7 12 13 36

0 6 37

1 2 5 38

0 4 39

2 5 7 9 40

1 13 41.

7. The method of claim 6 , further comprising:

determining the size Z of the matrices for the LDPC decoding.

8. The method of claim 7 , wherein the size Z is determined as one of values given below:

Z1′={3, 6, 12, 24, 48, 96, 192, 384}

Z2′={11, 22, 44, 88, 176, 352}

Z3′={5, 10, 20, 40, 80, 160, 320}

Z4′={9, 18, 36, 72, 144, 288}

Z5′={2, 4, 8, 16, 32, 64, 128, 256}

Z6′={15, 30, 60, 120, 240}

Z7′={7, 14, 28, 56, 112, 224}

Z8′={13, 26, 52, 104, 208}.

9. The method of claim 7 , wherein the obtaining the first matrix further comprises:

performing a modulo operation between the size Z and a shift value for each of the non-zero matrices associated with the second information; and

obtaining the each of the non-zero matrices that is a circulant permutation matrix based on a result of the modulo operation.

10. The method of claim 6 , wherein the first information is capable of indicating positions of the non-zero matrices of up to 42 rows and 52 columns.

11. A transmitter performing channel encoding in a communication system, the transmitter comprising:

a transceiver; and

a controller configured to control to:

identify a bit sequence to which low density parity check (LDPC) encoding is to be applied,

obtain a first matrix based on first information and second information, wherein the first matrix consists of matrices of size Z×Z,

obtain an encoded bit sequence by performing the LDPC encoding on the bit sequence based on the first matrix, and

transmit, to a receiver via the transceiver, the encoded bit sequence,

wherein the first information indicates position information on non-zero matrices among the matrices of size Z×Z in the first matrix,

wherein the second information indicates information on shift values for the non-zero matrices, and

wherein the first information includes thirty-two rows corresponding to a sequence given below:

0 1 2 3 6 9 10 11

0 3 4 5 6 7 8 9 11 12

0 1 3 4 8 10 12 13

1 2 4 5 6 7 8 9 10 13

0 1 11 14

0 1 5 7 11 15

0 5 7 9 11 16

1 5 7 11 13 17

0 1 12 18

1 8 10 11 19

0 1 6 7 20

0 7 9 13 21

1 3 11 22

0 1 8 13 23

1 6 11 13 24

0 10 11 25

1 9 11 12 26

1 5 11 12 27

0 6 7 28

0 1 10 29

1 4 11 30

0 8 13 31

1 2 32

0 3 5 33

1 2 9 34

0 5 35

2 7 12 13 36

0 6 37

1 2 5 38

0 4 39

2 5 7 9 40

1 13 41.

12. The transmitter of claim 11 , wherein the controller is further configured to determine the size Z of the matrices, based on a size of the bit sequence.

13. The transmitter of claim 12 , wherein the size Z is determined as one of values given below:

Z1′={3, 6, 12, 24, 48, 96, 192, 384}

Z2′={11, 22, 44, 88, 176, 352}

Z3′={5, 10, 20, 40, 80, 160, 320}

Z4′={9, 18, 36, 72, 144, 288}

Z5′={2, 4, 8, 16, 32, 64, 128, 256}

Z6′={15, 30, 60, 120, 240}

Z7′={7, 14, 28, 56, 112, 224}

Z8′={13, 26, 52, 104, 208}.

14. The transmitter of claim 12 , wherein the controller is further configured to:

perform a modulo operation between the size Z and a shift value for each of the non-zero matrices associated with the second information; and

obtain the each of the non-zero matrices that is a circulant permutation matrix based on a result of the modulo operation.

15. The transmitter of claim 11 , wherein the first information is capable of indicating positions of the non-zero matrices of up to 42 rows and 52 columns.

16. A receiver performing channel decoding in a communication system, the receiver comprising:

a transceiver; and

a controller configured to:

receive, from a transmitter via the transceiver, a signal,

obtain a first matrix based on first information and second information, wherein the first matrix consists of matrices of size Z×Z,

perform low density parity check (LDPC) decoding on a first sequence corresponding to the received signal based on the first matrix, and

obtaining a second bit sequence by the LDPC decoding,

wherein the first information indicates position information on non-zero matrices among the matrices of size Z×Z in the first matrix,

wherein the second information indicates information on shift values for the non-zero matrices, and

wherein the first information includes thirty-two rows corresponding to a sequence given below:

0 1 2 3 6 9 10 11

0 3 4 5 6 7 8 9 11 12

0 1 3 4 8 10 12 13

1 2 4 5 6 7 8 9 10 13

0 1 11 14

0 1 5 7 11 15

0 5 7 9 11 16

1 5 7 11 13 17

0 1 12 18

1 8 10 11 19

0 1 6 7 20

0 7 9 13 21

1 3 11 22

0 1 8 13 23

1 6 11 13 24

0 10 11 25

1 9 11 12 26

1 5 11 12 27

0 6 7 28

0 1 10 29

1 4 11 30

0 8 13 31

1 2 32

0 3 5 33

1 2 9 34

0 5 35

2 7 12 13 36

0 6 37

1 2 5 38

0 4 39

2 5 7 9 40

1 13 41.

17. The receiver of claim 16 , wherein the controller is further configured to determine the size Z of the matrices for the LDPC decoding.

18. The receiver of claim 17 , wherein the size Z is determined as one of values given below:

Z1′={3, 6, 12, 24, 48, 96, 192, 384}

Z2′={11, 22, 44, 88, 176, 352}

Z3′={5, 10, 20, 40, 80, 160, 320}

Z4′={9, 18, 36, 72, 144, 288}

Z5′={2, 4, 8, 16, 32, 64, 128, 256}

Z6′={15, 30, 60, 120, 240}

Z7′={7, 14, 28, 56, 112, 224}

Z8′={13, 26, 52, 104, 208}.

19. The receiver of claim 17 , wherein the controller is further configured to:

perform a modulo operation between the size Z and a shift value for each of the non-zero matrices associated with the second information; and

obtain the each of the non-zero matrices that is a circulant permutation matrix based on a result of the modulo operation.

20. The receiver of claim 16 , wherein the first information is capable of indicating positions of the non-zero matrices of up to 42 rows and 52 columns.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2018
From: AHN, SEOKKI; KIM, KYUNGJOONG; MYUNG, SEHO; JEONG, HONGSIL; JANG, MIN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 045724/0295 →
Priority Claims (3)
KR 10-2017-0057072 · May 4, 2017 · national
KR 10-2017-0071906 · Jun 8, 2017 · national
KR 10-2017-0075159 · Jun 14, 2017 · national
Continuity (1)
Related Publication 20180323807A1 · Nov 8, 2018