Semiconductor package

1. A semiconductor package comprising:

a connection member having a first surface and a second surface opposing the first surface, the connection member including a redistribution layer;

a support member disposed on the first surface of the connection member, including a cavity, the support member having an inner sidewall surrounding the cavity, and a chamfered upper region formed on a portion of the inner sidewall;

a semiconductor chip disposed on the connection member in the cavity and having connection pads electrically connected to the redistribution layer;

at least one electronic component disposed on a bottom surface of the cavity between the semiconductor chip and the chamfered upper region of the inner sidewall and having connection terminals electrically connected to the redistribution layer; and

an encapsulant encapsulating the semiconductor chip and the at least one electronic component disposed in the cavity,

wherein only the encapsulant is provided directly above an entirety of a lower surface of the chamfered upper region.

2. The semiconductor package of claim 1 , wherein the at least one electronic component is a plurality of electronic components, and

the chamfered upper region is a plurality of chamfered upper regions.

3. The semiconductor package of claim 2 , wherein the plurality of chamfered upper regions are arranged to correspond to the plurality of electronic components, respectively.

4. The semiconductor package of claim 1 , wherein the at least one electronic component is a plurality of electronic components, and

the plurality of electronic components are arranged along at least one side of the semiconductor chip.

5. The semiconductor package of claim 1 , wherein the chamfered upper region surrounds the cavity.

6. The semiconductor package of claim 1 , wherein portions of the inner sidewall do not include the chamfered upper region.

7. The semiconductor package of claim 1 , wherein the chamfered upper region has a step with respect to a lower region of the inner sidewall.

8. The semiconductor package of claim 7 , wherein a height of the lower region is three or less times the height of the electronic component adjacent to the inner sidewall.

9. The semiconductor package of claim 7 , wherein the step with respect to the lower region of the inner sidewall comprises a lower surface and a sloped side surface.

10. The semiconductor package of claim 1 , wherein the chamfered upper region has an inclined surface extending to the bottom a bottom surface of the cavity.

11. The semiconductor package of claim 1 , wherein the support member has a plurality of through-vias connected to the redistribution layer and extended to an upper surface thereof.

12. The semiconductor package of claim 11 , wherein the chamfered upper region is disposed between the plurality of through-vias.

13. The semiconductor package of claim 1 , wherein a portion of the support member in which the chamfered upper region is disposed has a width smaller than those of other portions of the support member.

14. The semiconductor package of claim 1 , wherein the chamfered upper region has a curved shape.

15. The semiconductor package of claim 1 , wherein the electronic component is a passive electronic component.

16. The semiconductor package of claim 1 , wherein the encapsulant is a resin layer.