Semiconductor device
A semiconductor device includes a first transistor formed on a substrate and including first and second impurity regions, a second transistor formed on the substrate and including a third impurity region electrically connected to the second impurity region, and a fourth impurity region, a power supply terminal electrically connected to the first impurity region, a ground terminal electrically connected to the fourth impurity region, a first guard ring surrounding the first transistor in a plan view and electrically connected to the ground terminal, and a second guard ring surrounding the second transistor in a plan view and electrically connected to the ground terminal. A conductivity type of the first through fourth impurity regions is different from a conductivity type of the first and second guard rings. The second guard ring has a width narrower than a width of the first guard ring in a plan view.
1. A semiconductor device comprising:
a substrate;
a first transistor formed on the substrate, and including a first impurity region of a first conductivity type, and a second impurity region of the first conductivity type;
a second transistor formed on the substrate, and including a third impurity region of the first conductivity type electrically connected to the second impurity region, and a fourth impurity region of the first conductivity type;
a power supply terminal electrically connected to the first impurity region;
a ground terminal electrically connected to the fourth impurity region;
a first guard ring of a second conductivity type different from the first conductivity type, formed on the substrate, surrounding the first transistor in a plan view, and electrically connected to the ground terminal; and
a second guard ring of the second conductivity type, formed on the substrate, surrounding the second transistor in a plan view, and electrically connected to the ground terminal,
wherein the first guard ring includes a first part having a longitudinal axis which extends in a first direction in the plan view,
wherein the second guard ring includes a second part having a longitudinal axis which extends in the first direction in the plan view, and
wherein a width of the second part along a second direction, which is perpendicular to the first direction, is narrower than a width of the first part along the second direction in a plan view.
2. The semiconductor device as claimed in claim 1 , further comprising:
at least one first via provided on the first guard ring, and the first via being a part of a route that electrically connects the first guard ring and the ground terminal; and
at least one second via provided on the second guard tine, and the second via being a part of a route that electrically connects the second guard ring and the ground terminal,
wherein number of the first vias provided in the second direction of the first guard ring is greater than number of the second vias provided in the second direction of the second guard ring.
3. The semiconductor device as claimed in claim 1 , further comprising:
a first wiring provided on the first guard ring and on the second guard ring, and the first wiring being a part of a route that electrically connects the first guard ring and the second guard ring to the ground terminal,
wherein a width of a first part of the first wiring positioned on the first guard ring, along the second direction, is wider than a width of a second part of the first wiring positioned on the second guard ring, along the second direction.
4. The semiconductor device as claimed in claim 1 , wherein the first impurity region is arranged at a position closer to the first guard ring than the second impurity region.
5. The semiconductor device as claimed in claim 1 , further comprising:
a power supply wiring, electrically connected to the power supply terminal, and arranged to overlap a plurality of the first transistors in a plan view; and
a ground wiring, electrically connected to the ground terminal, and arranged to overlap a plurality of the second transistors in a plan view.
6. The semiconductor device as claimed in claim 1 , further comprising:
a plurality of power supply wirings, electrically connected to the power supply terminal, and arranged to overlap a plurality of the first transistors in a plan view; and
a plurality of ground wirings, electrically connected to the ground terminal, and arranged to overlap a plurality of the second transistors and the plurality of the first transistors in a plan view,
wherein the power supply wirings on the plurality of the first transistors and the plurality of ground wirings on the plurality of the first transistors are alternately arranged in a plan view.
7. The semiconductor device as claimed in claim 1 , wherein the first transistor and the second transistor are Fin FETs (Field-Effect-Transistors).
8. The semiconductor device as claimed in claim 1 , wherein the first transistor and the second transistor are nanowire FETs (Field-Effect-Transistors).
9. The semiconductor device as claimed in claim 8 , wherein the first guard ring and the second guard ring have a plate-shaped structure, excluding a nanowire structure.