Connection system of semiconductor packages using a printed circuit board
A connection system of semiconductor packages includes: a printed circuit board; a first semiconductor package disposed on a first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; a second semiconductor package disposed on a second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures; and a third semiconductor package disposed on the first semiconductor package and connected to the first semiconductor package through third electrical connection structures. The first semiconductor package includes an application processor (AP), the second semiconductor package includes a memory, and the third semiconductor package includes a power management integrated circuit (PMIC).
1. A connection system of semiconductor packages, comprising:
a printed circuit board having a first surface and a second surface opposing the first surface;
a first semiconductor package disposed on the first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures;
a second semiconductor package disposed on the second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures; and
a third semiconductor package disposed on the first semiconductor package and connected to the first semiconductor package through third electrical connection structures,
wherein the first semiconductor package includes:
an application processor (AP) having an active surface having connection pads disposed thereon, and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the AP;
a connection member disposed on the active surface of the AP and including a redistribution layer electrically connecting the connection pads of the AP; and
the first electrical connection structures disposed on the other surface of the connection member opposing one surface of the connection member on which the AP is disposed and electrically connecting the redistribution layer to the printed circuit board,
wherein the second semiconductor package includes a memory,
wherein the third semiconductor package includes a power management integrated circuit (PMIC), and
wherein the active surface of the AP is interposed between the printed circuit board and the inactive surface of the AP.
2. The connection system of semiconductor packages of claim 1 , wherein the first semiconductor package and the second semiconductor package are disposed to face each other with the printed circuit board interposed therebetween.
3. The connection system of semiconductor packages of claim 1 , wherein the first semiconductor package further includes openings penetrating through the encapsulant, and
the third electrical connection structures are disposed in the openings of the encapsulant, and are electrically connected to the redistribution layer of the connection member.
4. The connection system of semiconductor packages of claim 1 , wherein the first semiconductor package further includes a core member having a through-hole,
the AP is disposed in the through-hole, and
the core member includes a wiring layer electrically connected to the connection pads of the AP.
5. The connection system of semiconductor packages of claim 4 , wherein the core member includes a first insulating layer in contact with the connection member, a first wiring layer in contact with the connection member and embedded in the first insulating layer, a second wiring layer disposed on the other surface of the first insulating layer opposing one surface of the first insulating layer in which the first wiring layer is embedded, and first vias penetrating through the first insulating layer and electrically connecting the first and second wiring layers to each other, and
the first and second wiring layers are electrically connected to the connection pads of the AP.
6. The connection system of semiconductor packages of claim 5 , wherein the core member further includes a second insulating layer disposed on the first insulating layer and covering the second wiring layer, a third wiring layer disposed on the second insulating layer, and second vias penetrating through the second insulating layer and electrically connecting the second and third wiring layers to each other, and
the third wiring layer is electrically connected to the connection pads of the AP.
7. The connection system of semiconductor packages of claim 4 , wherein the core member includes a first insulating layer, first and second wiring layers disposed on opposite surfaces of the first insulating layer, respectively, and first vias penetrating through the first insulating layer and electrically connecting the first and second wiring layers to each other, and
the first and second wiring layers are electrically connected to the connection pads of the AP.
8. The connection system of semiconductor packages of claim 7 , wherein the core member further includes a second insulating layer disposed on the first insulating layer and covering the first wiring layer, a third wiring layer disposed on the second insulating layer, second vias penetrating through the second insulating layer and electrically connecting the first and third wiring layers to each other, a third insulating layer disposed on the first insulating layer and covering the second wiring layer, a fourth wiring layer disposed on the third insulating layer, and third vias penetrating through the third insulating layer and electrically connecting the second and fourth wiring layers to each other, and
the third and fourth wiring layers are electrically connected to the connection pads of the AP.
9. A connection system of semiconductor packages, comprising:
a printed circuit board having a first surface and a second surface opposing the first surface;
a first semiconductor package disposed on the first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures;
a second semiconductor package disposed on the second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures;
and
a third semiconductor package disposed on the first semiconductor package and connected to the first semiconductor package through third electrical connection structures,
wherein the first semiconductor package includes an application processor (AP), the second semiconductor package includes a memory, and the third semiconductor package includes a power management integrated circuit (PMIC), and
wherein the second semiconductor package includes a connection member, including a redistribution layer, a first memory disposed on the connection member and electrically connected to the redistribution layer, a second memory disposed on the first memory and electrically connected to the redistribution layer, an encapsulant encapsulating at least portions of the first memory and the second memory, and the second electrical connection structures disposed on the other surface of the connection member opposing one surface of the connection member on which the first memory is disposed and electrically connecting the redistribution layer to the printed circuit board.
10. The connection system of semiconductor packages of claim 9 , wherein the first and second memories are connected to the redistribution layer by bonding wires.
11. The connection system of semiconductor packages of claim 9 , wherein the first and second memories are connected to the redistribution layer through vias.
12. The connection system of semiconductor packages of claim 1 , wherein the third semiconductor package includes the PMIC having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, an encapsulant encapsulating at least portions of the PMIC, a connection member disposed on the active surface of the PMIC and including a redistribution layer electrically connecting the connection pads of the PMIC, and the third electrical connection structures.
13. The connection system of semiconductor packages of claim 12 , wherein the third semiconductor package further includes passive components disposed side by side with the PMIC on one surface of the connection member on which the PMIC is disposed and at least partially encapsulated by the encapsulant.
14. The connection system of semiconductor packages of claim 12 , wherein the third semiconductor package further includes a core member having a through-hole, and
the PMIC is disposed in the through-hole.
15. The connection system of semiconductor packages of claim 14 , wherein the core member includes a first insulating layer, first and second wiring layers disposed on opposite surfaces of the first insulating layer, respectively, and first vias penetrating through the first insulating layer and electrically connecting the first and second wiring layers to each other, and
the first and second wiring layers are electrically connected to the connection pads of the PMIC.
16. The connection system of semiconductor packages of claim 15 , wherein the third electrical connection structures are disposed on the other surface of the core member opposing one surface of the core member on which the connection member is disposed, and are electrically connected to the second wiring layer of the core member.
17. The connection system of semiconductor packages of claim 1 , further comprising a plurality of passive components disposed on the second surface of the printed circuit board.
18. The connection system of semiconductor packages of claim 1 , further comprising a heat pipe disposed on the third semiconductor package.