Scalable excitatory and inhibitory neuron circuitry based on vanadium dioxide relaxation oscillators

1. A neural circuit comprising:

a first neuron circuit, comprising first and second resistively coupled relaxation oscillators, the first and second relaxation oscillators comprising respectively first and second passive load resistors in series with first and second locally-active current-controlled negative differential resistance devices, in series with first and second DC opposite voltage sources, in parallel with first and second grounded capacitors;

said first relaxation oscillator being also coupled to an input node of the first neuron circuit by a first load resistor and the first DC voltage source being a first, negative, voltage source; and

the second DC voltage source being a positive, voltage source;

the second relaxation oscillator being also coupled to an output node of the first neuron circuit;

a second neuron circuit, comprising third and fourth resistively coupled relaxation oscillators, the third and fourth relaxation oscillators comprising respectively third and fourth passive load resistors in series with third and fourth locally-active current-controlled negative differential resistance devices, in series with third and fourth DC opposite voltage sources, in parallel with third and fourth grounded capacitors; wherein:

said third relaxation oscillator is also coupled to an input node of the second neuron circuit by a third load resistor and the third DC voltage source is a third, positive, voltage source; and

said fourth DC voltage source being a fourth, negative, voltage source;

said fourth relaxation oscillator is also coupled to an output node of the second neuron circuit;

the first and second neuron circuits being connected in series.

2. A neural circuit comprising:

a first neuron circuit comprising first and second resistively coupled relaxation oscillators, the first and second relaxation oscillators comprising respectively first and second passive load resistors in series with first and second locally-active current-controlled negative differential resistance devices, in series with first and second DC opposite voltage sources, in parallel with first and second grounded capacitors; wherein:

said first relaxation oscillator is coupled to an input node of the first neuron circuit by a first load capacitor and said first DC voltage source is a first, negative, voltage source; and

said second DC voltage source is a second, positive, voltage source; said second relaxation oscillator being also coupled to an output node of the first neuron circuit;

a second neuron circuit, comprising third and fourth resistively coupled relaxation oscillators, the third and fourth relaxation oscillators comprising respectively third and fourth passive load resistors in series with third and fourth locally-active current-controlled negative differential resistance devices, in series with third and fourth DC opposite voltage sources, in parallel with third and fourth grounded capacitors wherein:

said third relaxation oscillator is also coupled to an input node of the second neuron circuit by a third load capacitor and said third DC voltage source is a third, positive, voltage source; and

said fourth DC voltage source is a fourth, negative, voltage source; said fourth relaxation oscillator being coupled to an output node of the second neuron circuit;

the first and second neuron circuits being connected in series.

3. A neuron circuit comprising first and second resistively coupled relaxation oscillators, the first and second relaxation oscillators comprising respectively first and second passive load resistors in series with first and second locally-active current-controlled negative differential resistance devices, in series with first and second DC opposite voltage sources, in parallel with first and second grounded capacitors.

4. The neuron circuit of claim 3 , wherein said first DC voltage source is a negative voltage source and said second DC voltage source is a positive voltage source.

5. The neuron circuit of claim 3 , wherein said first DC voltage source is a positive voltage source and said second DC voltage source is a negative voltage source.

6. The neuron circuit of claim 3 , wherein at least one of the first and second locally active current controlled negative differential resistance devices comprises a resistance connected in series with a negative differential resistance material between first and second nodes.

7. The neuron circuit of claim 3 , wherein at least one of the first and second locally active current controlled negative differential resistance devices comprises a vanadium dioxide layer between first and second nodes.

8. The neuron circuit of claim 3 , wherein:

the first and second relaxation oscillators are resistively coupled at a first node of the first relaxation oscillator and a first node of the second relaxation oscillator;

said first node of said first relaxation oscillator being connected to an input node of the neuron circuit by a first load capacitor; and

said first node of said second relaxation oscillator, forming an output node of the neuron circuit.

9. The neuron circuit of claim 8 , wherein said first DC voltage source is a negative voltage source and said second DC voltage source is a positive voltage source.

10. The neuron circuit of claim 8 , wherein said first DC voltage source is a positive voltage source and said second DC voltage source is a negative voltage source.

11. The neuron circuit of claim 8 , further comprising a load resistance in series or in parallel with the first load capacitor.

12. The neuron circuit of claim 3 , wherein said first and second DC voltage sources are voltage sources arranged to bring the first and second locally-active current-controlled negative differential resistance devices to a bias voltage less than their respective Mott insulator-to-metal transition voltages.

13. A neural circuit comprising at least a neuron circuit of claim 8 , said neuron circuit having its input node arranged to receive an input pulse through an input impedance; and having its output node arranged to provide an output pulse through an output impedance.