Ferroelectric memory devices

1. A ferroelectric memory device comprising:

a substrate; and

a ferroelectric layer, a variable resistive memory layer and a gate electrode which are sequentially stacked on a surface of the substrate,

wherein the ferroelectric layer has any one of a plurality of different remanent polarization values depending on a resistive state of the variable resistive memory layer,

wherein the resistive state of the variable resistive memory layer varies according to a voltage applied between the gate electrode and the substrate, and

wherein an absolute value of a first voltage for switching a resistance value of the variable resistive memory layer is greater than an absolute value of a second voltage for switching polarization of the ferroelectric layer, and

wherein the gate electrode comprises at least one of a tungsten material, an aluminum material, a copper material, a tantalum material, a titanium material, a gold material, a silver material, a ruthenium material, an iridium material, a molybdenum material, a tungsten nitride material, an aluminum nitride material, a titanium nitride material, a tantalum nitride material, a molybdenum nitride material, a niobium nitride material, a titanium silicon nitride material, a titanium aluminum nitride material, a titanium boron nitride material, a zirconium silicon nitride material, a tungsten silicon nitride material, a tungsten boron nitride material, a zirconium aluminum nitride material, a molybdenum silicon nitride material, a molybdenum aluminum nitride material, a tantalum silicon nitride material, a tantalum aluminum nitride material, a ruthenium nitride material and a doped silicon material.

2. The ferroelectric memory device of claim 1 ,

wherein the variable resistive memory layer includes at least one of a titanium oxide material, an aluminum oxide material, a nickel oxide material, a copper oxide material, a zirconium oxide material, a manganese oxide material, a hafnium oxide material, a tungsten oxide material, a tantalum oxide material, a niobium oxide material and a ferrum oxide material.

3. The ferroelectric memory device of claim 2 ,

wherein the ferroelectric layer has a thickness of approximately 5 nm to approximately 15 nm; and

wherein the variable resistive memory layer has a thickness of approximately 5 nm to approximately 10 nm.

4. The ferroelectric memory device of claim 1 , wherein the variable resistive memory layer includes at least one of a PCMO(Pr 1-x Ca x MnO 3 , where, 0<x<1) material, a LCMO(La 1-x Ca x MnO 3 , where, 0<x<1) material, a BSCFO(Ba 0.5 Sr 0.5 Co 0.8 Fe 0.2 O 3-δ ) material, a YBCO(YBa 2 Cu 3 O 7-x , where, 0<x<1) material, a (Ba,Sr)TiO 3 (Cr, Nb-doped) material, a SrZrO 3 (Cr,V-doped) material, a (La, Sr)MnO 3 material, a Sr 1-x La x TiO 3 (where, 0<x<1) material, a La 1-x Sr x FeO 3 (where, 0<x<1) material, a La 1-x Sr x CoO 3 (where, 0<x<1) material, a SrFeO 2.7 material, a LaCoO 3 material, a RuSr 2 GdCu 2 O 3 material and a YBa 2 Cu 3 O 7 material.

5. The ferroelectric memory device of claim 1 , wherein the variable resistive memory layer includes at least one of a germanium-stibium-tellurium (GST) material, an arsenide-stibium-tellurium (As—Sb—Te) material, a tin-stibium-tellurium (Sn—Sb—Te) material, a tin-indium-stibium-tellurium (Sn—In—Sb—Te) material and an arsenide-germanium-stibium-tellurium (As—Ge—Sb—Te) material.

6. A ferroelectric memory device comprising:

a substrate;

a ferroelectric layer disposed on the substrate;

a variable resistive memory layer disposed on the ferroelectric layer;

a gate electrode disposed on the variable resistive memory layer; and

a source region and a drain region disposed in the substrate to be spaced apart from each other,

wherein an absolute value of a first voltage for switching a resistance value of the variable resistive memory layer is greater than an absolute value of a second voltage for switching polarization of the ferroelectric layer, and

wherein the ferroelectric layer includes at least one of a hafnium oxide material, a zirconium oxide material and a hafnium zirconium oxide material.

7. The ferroelectric memory device of claim 6 , wherein the ferroelectric layer further includes at least one of carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd) and lanthanum (La) as a dopant element.

8. A ferroelectric memory device comprising:

a substrate;

a ferroelectric layer disposed on the substrate;

a variable resistive memory layer disposed on the ferroelectric layer;

a gate electrode disposed on the variable resistive memory layer; and

a source region and a drain region disposed in the substrate to be spaced apart from each other,

wherein an absolute value of a first voltage for switching a resistance value of the variable resistive memory layer is greater than an absolute value of a second voltage for switching polarization of the ferroelectric layer, and

wherein the variable resistive memory layer includes at least one of a titanium oxide material, an aluminum oxide material, a nickel oxide material, a copper oxide material, a zirconium oxide material, a manganese oxide material, a hafnium oxide material, a tungsten oxide material, a tantalum oxide material, a niobium oxide material and a ferrum oxide material.