Sample and hold circuit with indefinite holding time
A device includes a capacitive digital to analog converter (CDAC) that further includes a plurality of capacitors to sample an analog input signal. The sampled analog input signal is converted into a digital signal and the digital signal is stored by a successive approximation register (SAR). Thereafter, the SAR regenerates the stored digital signal to a reset plurality of capacitors, and a comparator is configured as an amplifier to generate an equivalent analog voltage of the stored digital signal.
1. A sample and hold circuit comprising:
a capacitive digital to analog converter (CDAC) that comprises:
a plurality of capacitors to sample an analog input signal;
a ground coupled to the plurality of capacitors, wherein the ground provides resetting of the plurality of capacitors after the sampling of the analog input signal;
a comparator having a first input, a second input and an output wherein the first input is coupled to the plurality of capacitors, wherein the comparator converts the sampled analog input signal into a digital signal;
a successive approximation register (SAR) that receives and stores the digital signal wherein the SAR regenerates and couples the digital signal to the plurality of capacitors of the CDAC; and
a plurality of switches to connect the plurality of capacitors to the ground to reset the plurality of capacitors;
wherein when the plurality of capacitors is reset to ground, the second input of the comparator is directly coupled to the output of the comparator;
wherein the resetting is performed after the conversion of the sampled input signal into the digital signal.
2. The sample and hold circuit of claim 1 , wherein during a conversion mode, the digital signal is derived by comparing a voltage on of the plurality of capacitors to a biasing voltage (Vbias).
3. The sample and hold circuit of claim 1 further comprising a control signal that is provided by the SAR to the CDAC, wherein the control signal includes a clock signal with a rising edge that triggers the sampling by the CDAC.
4. The sample and hold circuit of claim 3 , wherein a falling edge of the clock signal triggers a conversion mode that includes the conversion of the sampled analog input signal into the digital signal.
5. A successive approximation register analog to digital converter (SAR ADC) comprising:
a plurality of capacitors to sample an analog input signal;
a comparator having a first input, a second input and an output wherein the first input is coupled to the plurality of capacitors, wherein the comparator converts the sampled analog input signal into a digital signal;
a successive approximation register (SAR) that stores the digital signal, wherein the SAR regenerates and couples the stored digital signal to the plurality of capacitors;
a plurality of switches to connect the plurality of capacitors to ground to reset the plurality of capacitors;
wherein when the plurality of capacitors is reset to ground, the second input of the comparator is directly coupled to the output of the comparator;
wherein the resetting is performed after the conversion of the sampled input voltage signal into the digital signal.
6. The SAR ADC of claim 5 , wherein the comparator derives the digital signal by comparing capacitor charges of the plurality of capacitors to a biasing voltage (Vbias).
7. The SAR ADC of claim 5 further comprising a control signal that is provided by the SAR to the plurality of capacitors, wherein the control signal includes a clock signal with a rising edge that triggers the sampling of the analog input signal.
8. The SAR ADC of claim 7 , wherein a falling edge of the clock signal triggers a conversion mode that includes the conversion of the sampled analog input signal into the digital signals.