Asynchronous successive approximation analog-to-digital converter and related methods and apparatus
An ultrasound device including an asynchronous successive approximation analog-to-digital converter and method are provided. The device includes at least one ultrasonic transducer, a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADC) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry, wherein a DAC update event following at least one bit conversion is synchronized to a corresponding DAC update event of at least one other ADC in the plurality of ADCs.
1. A method of operating an ultrasound device comprising a successive-approximation-register (SAR) analog-to-digital converter (ADC) coupled to one or more ultrasonic transducers, the method comprising:
receiving, by the SAR ADC, a first clock signal;
receiving, by the SAR ADC, an analog signal generated based on outputs from the one or more ultrasonic transducers;
generating, by the SAR ADC, first and second bits of a digital signal corresponding to the analog signal, wherein generation of the first bit is triggered in response to the first clock signal and generation of the second bit is triggered by generation of the first bit.
2. The method of claim 1 , wherein:
the method further comprises generating, by the SAR ADC, in response to generation of the first bit of the digital signal, a first change in a first control signal; and
generation of the second bit of the digital signal is triggered by a second change in the first control signal.
3. The method of claim 2 , wherein:
the SAR ADC comprises a register;
generating the first bit of the digital signal comprises changing a most-significant-bit control signal that controls updating of a first bit of the register; and
generating the first change in the first control signal comprises generating the first change in response to the change in the most-significant-bit control signal.
4. The method of claim 2 , wherein a time between the first change in the first control signal and the second change in the first control determines a delay between conversion of successive bits of the digital signal.
5. The method of claim 2 , wherein:
the SAR ADC comprises a digital-to-analog converter (DAC) and a comparator; and
the method further comprises comparing, with the comparator, the analog signal with an output signal of the DAC in response to the first control signal.
6. The method of claim 2 , wherein:
the SAR ADC comprises a sample-and-hold circuit; and
the method further comprises:
changing, by the SAR ADC, a second control signal in response to the first clock signal;
acquiring, by the sample-and-hold circuit, the analog signal in response to the second control signal; and
changing, by the SAR ADC, in response to the second control signal, the first control signal prior to generation of the first bit of the digital signal.
7. The method of claim 1 , wherein:
the SAR ADC comprises a sample-and-hold circuit; and
the method further comprises:
changing, by the SAR ADC, a first control signal in response to the first clock signal; and
acquiring, by the sample-and-hold circuit, the analog signal in response to the first control signal.
8. The method of claim 1 , further comprising:
receiving, by the SAR ADC, a second clock signal; and
initiating, by the SAR ADC, conversion of the analog signal in response to the second clock signal.
9. An apparatus comprising a successive-approximation-register (SAR) analog-to-digital converter (ADC) coupled to one or more ultrasonic transducers, wherein the SAR ADC is configured to:
receive, on a first clock input terminal, a first clock signal;
receive, on an analog input terminal, an analog signal generated based on outputs from the one or more ultrasonic transducers;
generate, on a first bit output terminal, a first bit of a digital signal corresponding to the analog signal in response to the first clock signal; and
trigger generation, on a second bit output terminal, of a second bit of the digital signal in response to generation of the first bit of the digital signal.
10. The apparatus of claim 9 , wherein:
the SAR ADC is further configured to generate, in response to generation of the first bit of the digital signal, a first change in a first control signal on a first control output terminal; and
the SAR ADC is configured to trigger generation of the second bit of the digital signal on the second bit output terminal by a second change in the first control signal.
11. The apparatus of claim 10 , wherein:
the SAR ADC comprises a register;
the SAR ADC is configured, when generating the first bit of the digital signal, to change a most-significant-bit control signal that controls updating of a first bit of the register; and
the SAR ADC is configured, when generating the first change in the first control signal, to generate the first change in response to the change in the most-significant-bit control signal.
12. The apparatus of claim 10 , wherein a time between the first change in the first control signal and the second change in the first control determines a delay between conversion of successive bits of the digital signal.
13. The apparatus of claim 10 , wherein:
the SAR ADC comprises a digital-to-analog converter (DAC) and a comparator; and
the comparator is configured to compare the analog signal with an output signal of the DAC in response to the first control signal.
14. The apparatus of claim 10 , wherein:
the SAR ADC comprises a sample-and-hold circuit;
the SAR ADC is further configured to change, on a second control output terminal, a second control signal in response to the first clock signal;
the sample-and-hold circuit is configured to acquire the analog signal in response to the second control signal; and
the SAR ADC is further configured to change, in response to the second control signal, the first control signal on the first control output terminal prior to generation of the first bit of the digital signal on the first bit output terminal.
15. The apparatus of claim 9 , wherein:
the SAR ADC comprises a sample-and-hold circuit;
the SAR ADC is further configured to change, on a first control output terminal, a first control signal in response to the first clock signal; and
the sample-and-hold circuit is configured to acquire the analog signal in response to the first control signal.
16. The apparatus of claim 9 , wherein the SAR ADC is further configured to:
receive, on a second clock input terminal, a second clock signal; and
initiate conversion of the analog signal in response to the second clock signal.
17. A method of operating an ultrasound device comprising a successive-approximation-register (SAR) analog-to-digital converter (ADC) coupled to one or more ultrasonic transducers, the method comprising:
receiving, by the SAR ADC, an analog signal generated based on outputs from the one or more ultrasonic transducers;
generating, by the SAR ADC, a first bit of a digital signal corresponding to the analog signal synchronously; and
generating, by the SAR ADC, a subsequent bit of the digital signal asynchronously.
18. The method of claim 17 , further comprising:
generating, by the SAR ADC, a second bit of the digital signal synchronously.
19. An apparatus comprising a successive-approximation-register (SAR) analog-to-digital converter (ADC) coupled to one or more ultrasonic transducers, wherein the SAR ADC is configured to:
receive, on an analog input terminal, an analog signal generated based on outputs from the one or more ultrasonic transducers;
generate, on a first bit output terminal, a first bit of a digital signal corresponding to the analog signal synchronously; and
generate, on a subsequent bit output terminal, a subsequent bit of the digital signal asynchronously.
20. The apparatus of claim 19 , wherein the SAR ADC is further configured to:
generate, on a second bit output terminal, a second bit of the digital signal synchronously.