Vertical field effect transistors with self aligned source/drain junctions

1. A method of controlling an effective gate length in a vertical field effect transistor, comprising:

forming a vertical fin on a substrate, wherein the vertical fin includes a dopant species;

forming a bottom spacer layer on the substrate adjacent to the vertical fin;

forming a dummy gate block adjacent to the vertical fin on the bottom spacer layer;

forming a top spacer adjacent to the vertical fin on the dummy gate block;

removing the dummy gate block to expose a portion of the vertical fin between the top spacer and bottom spacer layer;

forming an absorption layer on the exposed portion of the vertical fin;

heat treating the absorption layer and vertical fin to form a dopant modified absorption layer, wherein the heat treatment causes at least a portion of the dopant species to diffuse/segregate from the vertical fin to the absorption layer to form the dopant modified absorption layer; and

removing the dopant modified absorption layer.

2. The method of claim 1 , wherein the absorption layer is formed by a rapid thermal oxidation or atomic layer deposition (ALD).

3. The method of claim 1 , wherein the absorption layer is an in-situ steam generation (ISSG) oxide layer formed through wet oxidation of the exposed portion of the vertical fin.

4. The method of claim 1 , wherein the vertical fin includes the dopant species in a concentration in a range of about 1×10 18 atoms/cm −3 to about 1×10 20 atoms/cm −3 .

5. The method of claim 4 , further comprising forming a gate dielectric layer on the portion of the vertical fin exposed by removing the dopant modified absorption layer.

6. The method of claim 5 , further comprising forming a conductive gate layer on the gate dielectric layer.

7. The method of claim 6 , further comprising forming a top source/drain on the vertical fin.

8. The method of claim 7 , wherein the dummy gate block has a thickness in a range of about 10 nm to about 50 nm.

9. A method of controlling an effective gate length in a vertical field effect transistor, comprising:

forming a vertical fin layer on a substrate, wherein the vertical fin layer includes a dopant species;

forming a plurality of vertical fins from the vertical fin layer, wherein the vertical fins include the dopant species;

forming a bottom source/drain layer on the substrate adjacent to each of the plurality of vertical fins;

forming a bottom spacer layer on the bottom source/drain layer adjacent to each of the plurality of vertical fins;

forming a dummy gate block adjacent to each of the plurality of vertical fins on the bottom spacer layer;

forming a top spacer adjacent to each of the plurality of vertical fins on the dummy gate block;

removing the dummy gate blocks to expose a portion of each of the plurality of vertical fins between the top spacer and bottom spacer layer;

forming an absorption layer on the exposed portion of each of the plurality of vertical fins; and

heat treating the absorption layer and plurality of vertical fins to diffuse/segregate at least a portion of the dopant species from the vertical fins to the absorption layer to form a dopant modified absorption layer.

10. The method of claim 9 , further comprising removing the dopant modified absorption layer, and forming a gate dielectric layer on the portion of the vertical fin exposed by removing the dopant modified absorption layer.

11. The method of claim 10 , wherein the plurality of vertical fins are made of a semiconductor material selected from the group consisting of group IV semiconductors, group IV-IV semiconductors, group III-V semiconductors, and group II-VI semiconductors.

12. The method of claim 11 , wherein the vertical fins can have a width in a range of about 4 nm to about 20 nm.

13. The method of claim 11 , wherein the heat treatment is conducted at a temperature in a range of about 700° C. to about 1200° C.