Contoured package-on-package joint
A contoured package on package joint and a method for making the same are disclosed herein. A method for forming a device comprises providing a substrate having a package land and forming a mounting stud on the package land. A molded underfill is applied to the substrate and in contact with the mounting stud. A contoured stud surface is formed on the mounting stud is contoured and connecting member attached to the contoured stud surface with a second package attached to the connecting member. The connecting member may be solder and have a spherical shape. The contoured stud surface may be etched or mechanically formed to have a hemispherical shape conforming to the connecting member shape.
1. A semiconductor device comprising:
a first redistribution layer;
a substrate over the first redistribution layer;
a second redistribution layer electrically connected to the first redistribution layer through the substrate;
a first semiconductor die in physical contact with the second redistribution layer;
an encapsulant encapsulating the first semiconductor die;
a conductive via extending through the encapsulant, the conductive via comprising:
a first straight sidewall facing the first semiconductor die;
a second straight sidewall opposite the first straight sidewall; and
a curved surface extending from the first straight sidewall to the second straight sidewall; and
an external connector is physical contact with the curved surface.
2. The semiconductor device of claim 1 , wherein the external connector is a solder ball.
3. The semiconductor device of claim 2 , wherein the external connector is part of a second package.
4. The semiconductor device of claim 3 , wherein the second package comprises a second semiconductor die located on an opposite side of a package substrate from the external connector.
5. The semiconductor device of claim 1 , wherein the first semiconductor die comprises solder bumps in physical contact with the second redistribution layer.
6. The semiconductor device of claim 1 , wherein the encapsulant has a surface which is planar with the first semiconductor die.
7. The semiconductor device of claim 1 , wherein the second redistribution layer is electrically connected to the first redistribution layer by through substrate vias.
8. A semiconductor device comprising:
a first package comprising:
a first substrate;
one or more first through vias extending through the first substrate;
one or more via lands;
at least one semiconductor die electrically connected to the one or more via lands on a first side of the first substrate;
external connections located on a second side of the first substrate opposite the first side;
a second package comprising:
a second substrate;
one or more second through vias extending through the second substrate;
a first semiconductor die located on a first side of the second substrate, the first semiconductor die electrically connected to at least one of the one or more second through vias; and
a copper post located on the first side of the second substrate, the copper post comprising a first straight sidewall which intersects a curved surface that conforms to a shape of one of the external connections.
9. The semiconductor device of claim 8 , wherein the at least one semiconductor die comprises at least two semiconductor die.
10. The semiconductor device of claim 9 , wherein each one of the at least two semiconductor die is electrically connected to separate ones of the one or more via lands by a wire bond.
11. The semiconductor device of claim 8 , wherein the one of the external connections is a solder ball.
12. The semiconductor device of claim 8 , wherein the second package further comprises an encapsulant encapsulating the first semiconductor die.
13. The semiconductor device of claim 8 , wherein the shape of the one of the external connections is a spherical shape.
14. The semiconductor device of claim 8 , wherein the first package is mounted at a standoff height from the second package of 200 μm or less.
15. A semiconductor device comprising:
a first level comprising a first substrate and a first through via;
a second level over the first level, the second level comprising a redistribution layer;
a third level over the second level, the third level comprising an encapsulant, a first semiconductor die, and a through encapsulant via, wherein a sidewall of the through encapsulant via at the third level is perpendicular with the first substrate; and
a fourth level over the third level, the fourth level comprising a curved surface of the through encapsulant via, the encapsulant, and the first semiconductor die.
16. The semiconductor device of claim 15 , wherein the fourth level further comprises a portion of an external connection adjacent to the curved surface.
17. The semiconductor device of claim 16 , further comprising a fifth level over the fourth level, the fifth level comprising a package substrate and a second through substrate via.
18. The semiconductor device of claim 17 , further comprising a sixth level over the fifth level, the sixth level comprising a second semiconductor die, the second semiconductor die being electrically connected to the second through substrate via.
19. The semiconductor device of claim 18 , wherein the second semiconductor die is electrically connected to the second through substrate via through a wire bond.
20. The semiconductor device of claim 18 , further comprising a seventh level over the sixth level, the seventh level comprising a third semiconductor die different from the second semiconductor die.