IP Library › Granted Patent US 10,733,108
Granted Patent B2
US 10,733,108 · App. 15/980,523 · Granted Aug 4, 2020

Physical page tracking for handling overcommitted memory

Inventors: Vijay Bahirji (Hillsboro, OR); Amin Firoozshahian (Mountain View, CA); Mahesh Madhav (Portland, OR); Toby Opferman (Beaverton, OR); Omid Azizi (Redwood City, CA)
Assignee: Intel Corporation
G06F12/1009G06F12/0223G06F12/0246G06F2212/1044G06F2212/401
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Quick Facts
Patent No.
US 10,733,108
App. No.
15/980,523
Granted
Aug 4, 2020
Kind
B2
Abstract

A system for computer memory management that implements a memory pool table, the memory pool table including entries that describe a plurality of memory pools, each memory pool representing a group of memory pages related by common attributes; a per-page tracking table, each entry in the per-page tracking table used to related a memory page with a memory pool of the memory pool table; and processing circuitry to: scan each entry in the per-page tracking table and, for each entry: determine an amount of memory released if the memory page related with the entry is swapped; aggregate the amount of memory for the respective memory pool related with the memory page related with the entry in the per-page tracking table, to produce a per-pool memory aggregate; and output the per-pool memory aggregate for the memory pools related with the memory pages in the per-page tracking table.

Claims (40)

1. A system for computer memory management, the system comprising:

a first memory device to store a memory pool table, the memory pool table including entries that describe a plurality of memory pools, each memory pool representing a group of memory pages related by common attributes;

a second memory device to store a per-page tracking table, each entry in the per-page tracking table to relate a memory page with a memory pool of the memory pool table; and

processing circuitry to:

scan each entry in the per-page tracking table and, for each entry:

determine an amount of memory released if the memory page related with the entry is swapped; and

aggregate the amount of memory for the respective memory pool related with the memory page related with the entry in the per-page tracking table, to produce a per-pool memory aggregate; and

output the per-pool memory aggregate for the memory pools related with the memory pages in the per-page tracking table.

2. The system of claim 1 , wherein the memory pages of the per-page tracking table are subject to a memory reduction technique.

3. The system of claim 2 , wherein the memory reduction technique includes memory data compression.

4. The system of claim 2 , wherein the memory reduction technique includes memory deduplication.

5. The system of claim 1 , wherein the processing circuitry is further to:

sort the per-pool memory aggregates for the memory pools from a highest value to a lowest value.

6. The system of claim 1 , wherein an entry in the memory pool table is to include a memory pool index and pool attributes.

7. The system of claim 6 , wherein the pool attributes is a bitmap used to define the pool attributes of the entry in the memory pool table.

8. The system of claim 7 , wherein the pool attributes is a four-bit bitmap used to define whether a particular memory pool is a user pool or kernel pool, shared or not, standby or active, and paged or not paged.

9. The system of claim 1 , wherein an entry in the per-page tracking table is to include a page index, a memory pool index, and page attributes.

10. The system of claim 9 , wherein the page attributes define whether a particular memory page is locked or unlocked.

11. The system of claim 10 , wherein, to scan each entry in the per-page tracking table, the processing circuitry is to:

determine the entry indicates that the related page is locked, and

discontinue further processing of the entry in response to the related page being locked.

12. The system of claim 1 , wherein to scan each entry in the per-page tracking table, the processing circuitry is to:

determine the entry is related with a memory pool of interest; and

discontinue further processing of the entry in response to the entry not being related with the memory pool of interest.

13. The system of claim 12 , wherein to determine the entry is related with the memory pool of interest, the processing circuitry is to evaluate a priority threshold against a memory pool priority.

14. The system of claim 13 , wherein the memory pool priority is calculated from memory pool attributes stored in the memory pool table.

15. The system of claim 12 , wherein, to determine the entry is related with the memory pool of interest, the processing circuitry is to determine whether the memory pool related with the entry in the per-page tracking table is in a list of memory pools to process.

16. The system of claim 15 , wherein the list of memory pools to process is provided to the processing circuitry from operating system software.

17. A method of computer memory management, the method comprising:

accessing a memory pool table, the memory pool table including entries that describe a plurality of memory pools, each memory pool representing a group of memory pages related by common attributes;

accessing a per-page tracking table, each entry in the per-page tracking table used to related a memory page with a memory pool of the memory pool table; and

scanning each entry in the per-page tracking table and, for each entry:

determining an amount of memory released if the memory page related with the entry is swapped; and

aggregating the amount of memory for the respective memory pool related with the memory page related with the entry in the per-page tracking table, to produce a per-pool memory aggregate; and

outputting the per-pool memory aggregate for the memory pools related with the memory pages in the per-page tracking table.

18. The method of claim 17 , wherein scanning each entry in the per-page tracking table comprises:

determining the entry is related with a memory pool of interest; and

discontinuing further processing of the entry in response to the entry not being related with the memory pool of interest.

19. The method of claim 18 , wherein determining the entry is related with the memory pool of interest comprises evaluating a priority threshold against a memory pool priority.

20. The method of claim 19 , wherein the memory pool priority is calculated from memory pool attributes stored in the memory pool table.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2019
From: BAHIRJI, VIJAY; FIROOZSHAHIAN, AMIN; MADHAV, MAHESH; OPFERMAN, TOBY; AZIZI, OMID
To: INTEL CORPORATION
Reel/Frame 049590/0860 →
Continuity (1)
Related Publication 20190354487A1 · Nov 21, 2019