IP Library Granted Patent US 10,262,931
Granted Patent B2
US 10,262,931 · App. 15/980,546 · Granted Apr 16, 2019

Lateral vias for connections to buried microconductors and methods thereof

Inventors: David P. Adams (Albuquerque, NM); Kira L. Fishgrab (Albuquerque, NM); Karl Douglas Greth (Albuquerque, NM); Michael David Henry (Albuquerque, NM); Jeffrey Stevens (Albuquerque, NM); V. Carter Hodges (Albuquerque, NM); Randy J. Shul (Albuquerque, NM); Ronald S. Goeke (Albuquerque, NM); Robert K. Grubbs (Boise, ID); Scott Silverman (San Marcos, CA)
Assignees: National Technology & Engineering Solutions of Sandia, LLC; Varioscale, Inc.
H01L23/49827H01L21/4803H01L21/486H01L21/4853H01L21/76898H01L23/481H01L23/5386H01L24/25H01L25/065H01L23/147H01L23/3121H01L23/49822H01L23/5384H01L24/13H01L24/16H01L2224/13009H01L2224/13101H01L2224/16145H01L2224/16225H01L2224/25105H01L2924/15311
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Quick Facts
Patent No.
US 10,262,931
App. No.
15/980,546
Granted
Apr 16, 2019
Kind
B2
Abstract

The present invention relates to a lateral via to provide an electrical connection to a buried conductor. In one instance, the buried conductor is a through via that extends along a first dimension, and the lateral via extends along a second dimension that is generally orthogonal to the first dimension. In another instance, the second dimension is oblique to the first dimension. Components having such lateral vias, as well as methods for creating such lateral vias are described herein.

Claims (34)

1. A method for creating a lateral via, the method comprising:

forming a microhole within a component comprising a buried conductor, wherein the microhole provides access to the buried conductor, wherein the component has a first longitudinal dimension extending between a top surface and a bottom surface of the component, wherein the microhole has a second longitudinal dimension extending along a length of the microhole, and wherein the second longitudinal dimension is generally orthogonal or oblique to the first longitudinal dimension; and

depositing a conductive material within the microhole to provide an electrical connection to the buried conductor, wherein the conductive material partially or completely fills the microhole.

2. The method of claim 1 , wherein the microhole comprises a length to width ratio of from about 100 to about 50,000.

3. The method of claim 1 , wherein the depositing step further comprises providing the electrical connection between the buried connector and a portion of a circuit board, and wherein the buried conductor comprises a through via.

4. The method of claim 1 , wherein the forming step comprises employing a laser to form the microhole, and wherein the employing step comprises pulsed laser ablation, chemically-assisted pulsed laser ablation, continuous wave laser-assisted chemical etching, and/or pulsed wave laser-assisted chemical etching.

5. The method of claim 1 , wherein the forming step comprises etching and ablation.

6. The method of claim 1 , further comprising, after the forming step:

depositing an insulative material within the microhole or a portion thereof, which comprises atomic layer deposition of the insulative material.

7. The method of claim 1 , wherein the depositing a conductive material step comprises atomic layer deposition of the conductive material and/or comprises local heating by way of laser irradiation.

8. The method of claim 1 , further comprising, before the forming step:

applying a sacrificial coating to an outer surface of the component.

9. The method of claim 8 , further comprising, after the applying step:

removing the sacrificial coating, thereby releasing the component having the lateral via.

10. The method of claim 1 , wherein the forming step comprises a laser-stimulated process.

11. The method of claim 10 , wherein the laser-stimulated process comprises an etchant.

12. The method of claim 11 , wherein the etchant comprises molecular chlorine.

13. The method of claim 12 , wherein the component comprises silicon.

14. The method of claim 1 , wherein the buried conductor comprises a through via or a solder bump.

15. The method of claim 1 , further comprising, before the forming step:

depositing a resist layer on a surface of the component; and

patterning the resist layer to form a patterned resist layer having apertures, wherein the apertures can be etched during the forming step.

16. A method for creating a lateral via, the method comprising:

removing an edge of a component;

applying a coating on the component;

providing a clearance hole within the coating;

forming a microhole within the component comprising a buried conductor, wherein the microhole provides access to the buried conductor, wherein the component has a first longitudinal dimension extending between a top surface and a bottom surface of the component, wherein the microhole has a second longitudinal dimension extending along a length of the microhole, and wherein the second longitudinal dimension is generally orthogonal or oblique to the first longitudinal dimension;

depositing a conductive material within the microhole to provide an electrical connection to the buried conductor, wherein the conductive material partially or completely fills the microhole; and

removing the coating, thereby releasing the component including the later via.

17. The method of claim 16 , further comprising, after the forming step:

depositing an insulative material within the microhole or a portion thereof, which comprises atomic layer deposition of the insulative material.

18. The method of claim 16 , wherein the depositing step further comprises providing the electrical connection between the buried connector and a portion of a circuit board, and wherein the buried conductor comprises a through via.

19. The method of claim 16 , wherein the forming step comprises employing a laser to form the microhole, and wherein the employing step comprises pulsed laser ablation, chemically-assisted pulsed laser ablation, continuous wave laser-assisted chemical etching, and/or pulsed wave laser-assisted chemical etching.

20. The method of claim 16 , wherein the forming step comprises etching and ablation.

Assignments (4)
CONFIRMATORY LICENSE Recorded Jan 23, 2019
From: NATIONAL TECHNOLOGY & ENGINEERING SOLUTIONS OF SANDIA, LLC
To: U.S. DEPARTMENT OF ENERGY
Reel/Frame 048109/0473 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2018
From: ADAMS, DAVID P.; FISHGRAB, KIRA L.; GRETH, KARL DOUGLAS; HENRY, MICHAEL DAVID; STEVENS, JEFFREY; HODGES, V. CARTER; SHUL, RANDY J.; GOEKE, RONALD S.; GRUBBS, ROBERT K.
To: SANDIA CORPORATION
Reel/Frame 046881/0709 →
CHANGE OF NAME Recorded Sep 14, 2018
From: SANDIA CORPORATION
To: NATIONAL TECHNOLOGY & ENGINEERING SOLUTIONS OF SANDIA, LLC
Reel/Frame 047093/0352 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2018
From: SILVERMAN, SCOTT
To: VARIOSCALE, INC.
Reel/Frame 046868/0516 →
Continuity (2)
Division 15175312 · Jun 7, 2016
Related Publication 20180269143A1 · Sep 20, 2018