Methods for data acquisition systems in real time applications
A system may include a data acquisition hardware device (DAQ) for acquiring sample data and/or generating control signals, and a host system with memory that may store data samples and information associated with the DAQ and host system operations. The DAQ may push hardware status information to host memory, triggered by predetermined events taking place in the DAQ, e.g. timing events or interrupts. The DAQ may update dedicated buffers in host memory with status data for any of these events. The pushed status information may be read in a manner that allows detection of race conditions, and may be used to handle data acquisition, output control signaling, and interrupts as required without the host system having to query the DAQ. The DAQ may also detect data timing errors and report those data timing errors back to the host system, and also provide improved output operations using counters.
1. A peripheral device comprising:
a bus interface configured to facilitate communication of the peripheral device with a host system; and
an error detection circuit communicatively coupled to the bus interface and configured to perform data timing error detection, wherein in performing the data timing error detection, the error detection circuitry is configured to:
receive incoming data from the host system;
in response to expected first data of the incoming data not being available for a present sample clock period, report to the host system a first-type error corresponding to the present sample clock period and create a record of the reported first-type error;
in response to more than the expected first data being available for the present sample clock period, report to the host system a second-type error corresponding to the present sample clock period and create a record of the reported second-type error; and
report to the host system whether expected second data of the incoming data has been correctly received for a most recent previous sample clock period.
2. The peripheral device of claim 1 , wherein the error detection circuit is further configured to report to the host system whether the expected second data of the incoming data has been correctly received for the most recent previous sample clock period based at least in part on one or more of the following:
an indication of whether the error detection circuit has reported a first-type error corresponding to the most recent previous sample clock period to the host system; or
an indication of whether the error detection circuit has reported a second-type error corresponding to the most recent previous sample clock period to the host system.
3. The peripheral device of claim 1 , wherein the error detection circuitry is configured to perform one or more of the following:
delete the record of the reported first-type error in response to receiving an acknowledgment of the reported first-type error from the host system; or
delete the record of the reported second-type error in response to receiving an acknowledgment of the reported second-type error from the host system.
4. The peripheral device of claim 1 , wherein the error detection circuit is configured to perform the data timing error detection for each sample clock period of a plurality of sample clock periods that also comprise the present sample clock period and the next sample clock period.
5. The peripheral device of claim 1 , further comprising:
a first register, a second register, and a third register; and
a control circuit configured to:
generate an output signal, alternating between generating the output signal at least according to contents of the first register and generating the output signal at least according to contents of the second register;
copy contents of the third register into the first register when generating the output signal at least according to the contents of the second register;
copy the contents of the third register into the second register when generating the output signal at least according to the contents of the first register; and
update the contents of the third register with available data of the incoming data subsequent to having copied the contents of the third register into either the first register or the second register.
6. The peripheral device of claim 5 , wherein the output signal is a periodic signal.
7. The peripheral device of claim 5 , wherein a width of each pulse of the periodic signal and a time duration between subsequent pulses of the periodic signal are defined by the contents of:
the first register when the control circuitry is generating the periodic signal at least according to the contents of the first register; and
the second register when the control circuit is generating the periodic signal at least according to the contents of the second register.
8. The peripheral device of claim 5 , wherein the error detection circuitry is configured to:
report the first-type error to the host system in response to the third register having been updated with less than the expected first data between the most recent previous sample clock period and the present sample clock period; and
report the second-type error to the host system in response to the third register having been updated with more than the expected first data between the most recent previous sample clock period and the present sample clock period.
9. The peripheral device of claim 5 , wherein the control circuitry comprises a counter and wherein the output signal is an output of the counter.
10. A method for data timing error detection, the method comprising:
(a) receiving incoming data from a host system;
(b) in response to expected first data of the incoming data not being available for a present sample clock period:
reporting to the host system a first-type error corresponding to the present sample clock period; and
creating a record of the reported first-type error;
(c) in response to more than the expected first data being available for the present sample clock period:
reporting to the host system a second type error corresponding to the present sample clock period; and
creating a record of the reported second type error; and
(d) reporting to the host system whether expected second data of the incoming data has been correctly received for a most recent previous sample clock period.
11. The method of claim 10 , wherein said reporting to the host system whether the expected second data has been correctly received for the most recent previous sample clock period is performed based at least in part on one or more of:
an indication of whether a first-type error corresponding to the most recent previous sample clock period has been reported to the host system; or
an indication of whether a second-type error corresponding to the most recent previous sample clock period has been reported to the host system.
12. The method of claim 10 , further comprising:
deleting the record of the reported first-type error in response to receiving an acknowledgment of the reported first-type error from the host system; or
deleting the record of the reported second-type error in response to receiving an acknowledgment of the reported second-type error from the host system.
13. The method of claim 10 , wherein the present sample clock period and the most recent previous sample clock period are comprised in a plurality of sample clock periods, wherein the method further comprises:
performing (a) through (d) for each sample clock period of the plurality of sample clock periods.
14. A data acquisition system comprising:
a communication bus;
a host system coupled to the communication bus; and
a data acquisition device coupled to the communication bus and configured to:
receive incoming data over the communication bus from the host system; and
perform data timing error correction, wherein in performing the data timing error correction, the data acquisition device is configured to:
in response to expected first data of the incoming data not being available for a present sample clock period, report to the host system a first-type error corresponding to the present sample clock period and create a record of the reported first-type error;
in response to more than the expected first data being available for the present sample clock period, report to the host system a second-type error corresponding to the present sample clock period and create a record of the reported second-type error; and
report to the host system whether expected second data of the incoming data has been correctly received for a most recent previous sample clock period.
15. The data acquisition system of claim 14 , wherein the data acquisition device is further configured to report to the host system whether the expected second data of the incoming data has been correctly received for the most recent previous sample clock period based at least in part on one or more of:
an indication of whether the data acquisition device has reported a first-type error corresponding to the most recent previous sample clock period to the host system; or
an indication of whether the data acquisition device has reported a second-type error corresponding to the most recent previous sample clock period to the host system.
16. The data acquisition system of claim 14 , wherein the control circuitry is configured to update the contents of the third register with update data received from the host system through the communication bus.
17. The data acquisition system of claim 16 , wherein the data acquisition device is further configured to:
delete the record of the reported first-type error in response to receiving an acknowledgment of the reported first-type error from the host system; or
delete the record of the reported second-type error in response to receiving an acknowledgment of the reported second-type error from the host system.
18. The data acquisition system of claim 17 , wherein the present sample clock period and the most recent previous sample clock period are comprised in a plurality of sample clock periods;
wherein the data acquisition device is configured to perform the data timing error detection for each sample clock period of the plurality of sample clock periods.
19. The data acquisition system of claim 15 , wherein the data acquisition device comprises:
a first register, a second register, and a third register; and
a control circuit configured to:
generate an output signal, alternating between generating the output signal at least according to contents of the first register and generating the output signal at least according to contents of the second register;
copy contents of the third register into the first register when generating the output signal at least according to the contents of the second register;
copy the contents of the third register into the second register when generating the output signal at least according to the contents of the first register;
update the contents of the third register with available data of the incoming data subsequent to having copied the contents of the third register into either the first register or the second register;
report the first-type error to the host system in response to the third register having been updated with less than the expected first data between the most recent previous sample clock period and the present sample clock period; and
report the second-type error to the host system in response to the third register having been updated with more than the expected first data between the most recent previous sample clock period and the present sample clock period.