IP Library Granted Patent US 10,483,192
Granted Patent B2
US 10,483,192 · App. 15/982,616 · Granted Nov 19, 2019

Packaged semiconductor devices with laser grooved wettable flank and methods of manufacture

Inventors: Aira Lourdes Villamor (Lapu-Lapu, PH); Erwin Victor Cruz (Koronadal, PH); Geraldine Suico (Consolacion, PH); Silnore Sabando (Lapu-Lapu, PH)
Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
H01L23/49544H01L21/4821H01L21/4842H01L21/561H01L23/3157H01L23/492H01L23/4952H01L23/49548H01L23/49575H01L23/49582H01L23/3107
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Quick Facts
Patent No.
US 10,483,192
App. No.
15/982,616
Granted
Nov 19, 2019
Kind
B2
Abstract

In a general aspect, a method for producing a packaged semiconductor device can include coupling a semiconductor device to a leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The method can also include encapsulating at least a portion of the semiconductor device and at least a portion of the leadframe structure in a molding compound. At least a segment of the signal lead can be exposed outside the molding compound. A surface of the molding compound can define a primary plane of the packaged semiconductor device. The method can further include forming, with a laser, a groove in the segment, applying solder plating to the segment, including the groove, and separating, at the groove, the segment into a first portion and a second portion, such that the second portion of the segment is separated from the leadframe structure.

Claims (41)

1. A method of producing a packaged semiconductor device, the method comprising:

coupling a semiconductor device to a metal leadframe structure, the metal leadframe structure having a signal lead that is electrically coupled with the semiconductor device;

encapsulating at least a portion of the semiconductor device and at least a portion of the metal leadframe structure in a molding compound, at least a segment of the signal lead being exposed outside the molding compound, a surface of the molding compound defining a primary plane of the packaged semiconductor device;

forming, with a laser, a groove in the segment of the signal lead;

applying solder plating to the segment of the signal lead, including the groove; and

separating, at the groove, the segment of the signal lead into a first portion and a second portion, such that the second portion of the segment of the signal lead is separated from the metal leadframe structure,

the separating the segment of the signal lead defines a signal lead flank on an end of the first portion of the segment of the signal lead, the signal lead flank having a surface area, a first portion of the surface area of the signal lead flank being defined by the solder plating, and a second portion of the surface area of the flank of the signal lead defined by exposed metal of the metal leadframe structure.

2. The method claim 1 , wherein a center portion of the surface of the exposed metal has a height along an axis that is approximately orthogonal with the primary plane of the packaged semiconductor device, the height of the center portion being greater than a height, along the axis that is approximately orthogonal with the primary plane of the packaged semiconductor device, of a portion of the surface of the exposed metal that is laterally disposed from the center portion of the surface of the exposed metal.

3. The method of claim 1 , wherein a perimeter of the surface of the exposed metal has at least one curved edge.

4. The method of claim 1 , wherein a perimeter of the surface of the exposed metal is semicircle shaped.

5. The method of claim 1 , wherein the surface of the exposed metal is surrounded by the solder plating.

6. A method of producing a packaged semiconductor device, the method comprising:

coupling a semiconductor device to a metal leadframe structure, the metal leadframe structure having a signal lead that is electrically coupled with the semiconductor device;

encapsulating at least a portion of the semiconductor device and at least a portion of the metal leadframe structure in a molding compound, at least a segment of the signal lead being exposed outside the molding compound, a surface of the molding compound defining a primary plane of the packaged semiconductor device;

forming, with a laser, a groove in the segment of the signal lead;

applying a solder plating to the segment of the signal lead, including the groove; and

separating, at the groove, the segment of the signal lead into a first portion and a second portion, such that the second portion of the segment of the signal lead is separated from the metal leadframe structure and a flank of the signal lead is defined at an end of the first portion of the segment of the signal lead,

wherein the flank of the signal lead has a surface area, the surface area of the flank of the signal lead having a first portion and a second portion, the first portion being defined by the groove, the second portion being defined by the separation of the segment of the signal lead into the first portion and the second portion, exposed metal leadframe structure being included in the second portion of the surface area of the flank.

7. The method of claim 6 , wherein:

the first portion of the surface area of the flank of the signal lead includes at least 75% of the surface area of the flank of the signal lead, and is defined by the solder plating, and

the second portion of the surface area of the flank of the signal lead includes 25% or less of the surface area of the flank of the signal lead, and is defined by exposed metal of the metal leadframe structure.

8. The method of claim 7 , wherein a perimeter of a surface of the exposed metal has at least one curved edge.

9. The method of claim 6 , wherein separating the segment of the signal lead includes cleaving the metal leadframe structure.

10. The method of claim 6 , wherein separating the segment of the signal lead includes sawing the metal leadframe structure.

11. The method of claim 6 , wherein:

wherein the first portion of the surface area of the flank of the signal lead is defined by the solder plating, and the second portion of the surface area of the flank of the signal lead is defined by exposed metal of the metal leadframe structure; and

the molding compound defines a primary plane of the packaged semiconductor device, a center portion of a cross-sectional profile of the surface of the exposed metal of the second portion of the surface area the flank of the signal lead having a height along an axis that is approximately orthogonal to the primary plane of the packaged semiconductor device, the height of the center portion being greater than a height of a portion of the cross-sectional profile of the surface of the exposed metal of the second portion of the surface area of the flank of the signal lead that is laterally disposed from the center portion.

12. The method of claim 11 , wherein a perimeter of a surface of the exposed metal is crescent shaped.

13. The method of claim 11 , wherein a perimeter of a surface of the exposed metal is semicircle shaped.

14. The method of claim 6 , wherein the portion of the signal lead that is exposed outside the molding compound extends away from a surface of the molding compound, such that the flank of the signal lead is spaced a distance from the surface of the molding compound.

15. The method of claim 6 , wherein the flank of the signal lead is substantially coplanar with a surface of the molding compound.

16. A method of producing a packaged semiconductor device, the method comprising:

coupling a semiconductor device to a metal leadframe structure, the metal leadframe structure having a signal lead that is electrically coupled with the semiconductor device;

encapsulating at least a portion of the semiconductor device and at least a portion of the metal leadframe structure in a molding compound, at least a segment of the signal lead being exposed outside the molding compound, a surface of the molding compound defining a primary plane of the packaged semiconductor device;

forming, with a laser, a groove in the segment of the signal lead;

applying a solder plating to the segment of the signal lead, including the groove; and

separating, at the groove, the segment of the signal lead into a first portion and a second portion, such that the second portion of the segment of the signal lead is separated from the metal leadframe structure and a flank of the signal lead is defined at an end of the first portion of the segment of the signal lead,

the flank of the signal lead having a surface area, a first portion of the surface area of the flank of the signal lead being defined by the solder plating, and a second portion of the surface area of the flank of the signal lead being defined by exposed metal of the metal leadframe structure, the surface area of the flank being a discontinuous surface area, a perimeter of a surface of the exposed metal being crescent shaped or semicircular shaped, a center portion of the surface of the exposed metal having a height along an axis that is approximately orthogonal with a primary plane of the packaged semiconductor device, the primary plane of the packaged semiconductor device being defined by the molding compound, the height of the center portion being greater than a height, along the axis that is approximately orthogonal with the primary plane of the packaged semiconductor device, of a portion of the surface of the exposed metal that is laterally disposed from the center portion of the surface of the exposed metal.

17. The method of claim 16 , wherein the flank of the signal lead is disposed at an end of the signal lead, the discontinuous surface area of the flank including the first portion of the surface area of the flank of the signal lead and the second portion of the surface area of the flank of the signal lead, the first portion of the surface area of the flank of the signal lead being defined by the groove, the second portion of the surface area of the flank of the signal lead being defined by cleaving the metal leadframe structure, the surface of the exposed metal being included in the second portion of the surface area of the flank of the signal lead.

18. The method of claim 17 , the discontinuous surface area of the flank further including a third portion disposed between the first portion of the discontinuous surface area of the flank and the second portion of the discontinuous surface area of the flank.

19. The method of claim 16 , wherein the flank of the signal lead is disposed at an end of the signal lead, the discontinuous surface area of the flank including the first portion of the surface area of the flank of the signal lead and the second portion of the surface area of the flank of the signal lead, the first portion of the surface area of the flank of the signal lead being defined by the groove, the second portion of the surface area of the flank of the signal lead being defined by sawing the metal leadframe structure, the surface of the exposed metal being included in the second portion of the surface area of the flank of the signal lead.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 047864, FRAME 0611 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064077/0298 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Oct 16, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047864/0611 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2018
From: VILLAMOR, AIRA LOURDES; SUICO, GERALDINE; CRUZ, ERWIN VICTOR; SABANDO, SILNORE
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 046183/0406 →
Continuity (2)
Continuation 15407918 · Jan 17, 2017
Related Publication 20180269138A1 · Sep 20, 2018